tangxifan
|
148da80869
|
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
|
2021-04-24 14:53:29 -06:00 |
|
tangxifan
|
96ce6b545f
|
[Tool] Patch repack to consider design constraints for pins that are not equivalent
|
2021-04-21 13:53:08 -06:00 |
|
tangxifan
|
5364b94cf8
|
[Tool] Update bitstream setting parser/writer to support interconnect-related syntax
|
2021-04-19 13:42:12 -06:00 |
|
tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
|
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
|
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
|
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
|
tangxifan
|
d877a02534
|
[Tool] Patch the extended bitstream setting support on mode-select bits
|
2021-03-10 21:28:09 -07:00 |
|
tangxifan
|
85640a7403
|
[Tool] Extend bitstream setting to support mode bits overload from eblif file
|
2021-03-10 20:45:48 -07:00 |
|
tangxifan
|
e34380a654
|
Merge branch 'master' into default_net_type
|
2021-03-01 08:38:58 -07:00 |
|
tangxifan
|
73461971d2
|
[Tool] Bug fix for printing single-bit ports in Verilog netlists
|
2021-02-28 16:12:57 -07:00 |
|
tangxifan
|
7a5dd1bc02
|
[Tools] Patch circuit library for dummy circuit models without any ports
|
2021-02-24 10:36:48 -07:00 |
|
tangxifan
|
b2984b46ee
|
[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
|
2021-02-09 21:15:57 -07:00 |
|
tangxifan
|
faabdab815
|
[Tool] Remove redundant tab in bitstream setting writer
|
2021-02-01 18:04:21 -07:00 |
|
tangxifan
|
d5b1cc5ec7
|
[Tool] Bug fix in parser for bitstream settings
|
2021-02-01 18:01:42 -07:00 |
|
tangxifan
|
f102e84497
|
[Tool] Add bitstream setting file to openfpga library
|
2021-02-01 17:43:46 -07:00 |
|
tangxifan
|
3b7762ef85
|
[Lib] Now try to call undefined command will cause a error code to return
|
2021-01-24 17:44:51 -07:00 |
|
tangxifan
|
a8158322ef
|
[Tool] Bug fix in setting command execution status in OpenFPGA shell
|
2021-01-24 17:25:03 -07:00 |
|
tangxifan
|
fd0e73a9bb
|
[Tool] Enhance return code for openfpga shell
|
2021-01-24 14:48:27 -07:00 |
|
tangxifan
|
8cac3291cb
|
[Tool] Add batch mode to openfpga shell execution
|
2021-01-24 14:33:58 -07:00 |
|
tangxifan
|
4cc8b08a6c
|
[Tool] Add openfpga version display
|
2021-01-23 16:38:00 -07:00 |
|
tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
|
tangxifan
|
ecd955124b
|
[Lib] Add libpcf to CMakelist and bug fix
|
2021-01-19 15:51:14 -07:00 |
|
tangxifan
|
52ac7826eb
|
[Lib] Add a library of parser/writer for pin constraint file (PCF)
|
2021-01-19 15:45:45 -07:00 |
|
tangxifan
|
ea9d6bfe91
|
[Flow] Update the design constraint file to follow bug fix in parser
|
2021-01-17 10:41:01 -07:00 |
|
tangxifan
|
113119bd8e
|
[Lib] Fix the bug in repack design constraint parser
|
2021-01-17 10:39:55 -07:00 |
|
tangxifan
|
2efe513122
|
[Tool] Now repack consider design constraints; test pending
|
2021-01-16 21:57:17 -07:00 |
|
tangxifan
|
d0e05b3575
|
[Lib] Now use pb_type in design constraints instead of physical tiles
|
2021-01-16 21:35:43 -07:00 |
|
tangxifan
|
b86adabe69
|
[Lib] Remove unused data storage from repack design constraints
|
2021-01-16 21:14:52 -07:00 |
|
tangxifan
|
706e84bb62
|
[Lib] Bug fix in testing program
|
2021-01-16 18:15:56 -07:00 |
|
tangxifan
|
67c54c4d3b
|
[Lib] Bug fix in the repack design constraint lib
|
2021-01-16 17:34:22 -07:00 |
|
tangxifan
|
ad7a54db1b
|
[Tool] Add repack dc library to compilation
|
2021-01-16 17:20:59 -07:00 |
|
tangxifan
|
9d80f1ab39
|
[Lib] Add test program to the library of repack design constraints
|
2021-01-16 17:18:42 -07:00 |
|
tangxifan
|
03b5bcc244
|
[Lib] Add XML writer for repack design constraints
|
2021-01-16 17:15:31 -07:00 |
|
tangxifan
|
2a7601fb7e
|
[Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints
|
2021-01-16 17:14:51 -07:00 |
|
tangxifan
|
f1bfa2ef8c
|
[Lib] Add XML parser for repack design constraints
|
2021-01-16 17:03:01 -07:00 |
|
tangxifan
|
8be12b6e82
|
[Lib] Add example design constraint file
|
2021-01-16 16:36:10 -07:00 |
|
tangxifan
|
a926c74ae5
|
[Lib] Add CMake script to compile the repack design constraint library
|
2021-01-16 16:35:46 -07:00 |
|
tangxifan
|
b57dc7b898
|
[Lib] Add repack design constraint library
|
2021-01-16 16:35:13 -07:00 |
|
tangxifan
|
b8e4675a3a
|
[Tool] Add missing file
|
2021-01-15 14:48:19 -07:00 |
|
tangxifan
|
87b2c1f3b8
|
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
|
2021-01-15 12:01:53 -07:00 |
|
tangxifan
|
852f5bb72e
|
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
|
2021-01-14 15:38:24 -07:00 |
|
tangxifan
|
4124777948
|
[Tool] Set (x,y) to be optional XML syntax in tile annotation
|
2021-01-09 18:56:41 -07:00 |
|
tangxifan
|
9a441fa5cc
|
[Tool] Upgrade openfpga to support extended global tile port definition
|
2021-01-09 18:47:12 -07:00 |
|
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
|
2021-01-04 17:14:26 -07:00 |
|
tangxifan
|
cb34be0dc0
|
[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements
|
2021-01-04 15:13:54 -07:00 |
|
tangxifan
|
d195b9e32c
|
[Tool] Bug fix in XML syntax to define default values for a global tile port
|
2020-12-02 17:03:48 -07:00 |
|
tangxifan
|
e959821813
|
[Tool] Enhance internal check functions for tile annotation
|
2020-11-11 13:59:24 -07:00 |
|
tangxifan
|
4dc0fb81c5
|
[Tool] Bug fix for clang compilation error
|
2020-11-10 20:32:58 -07:00 |
|
tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
67af145455
|
[Tool] Add XML writer for tile annotation
|
2020-11-10 14:51:46 -07:00 |
|
tangxifan
|
6fbdbe68ae
|
[Tool] Add tile annotation parser
|
2020-11-10 14:32:24 -07:00 |
|
tangxifan
|
0a273ffab6
|
[Tool] Bug fix in the tight requirements on CCFF circuit model
|
2020-11-06 11:16:46 -07:00 |
|
tangxifan
|
ba0120bd76
|
[Tool] Remove the limitation on requiring Qb ports for CCFF
|
2020-11-06 11:10:04 -07:00 |
|
tangxifan
|
37c10f0cb5
|
[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
f1ce816d6c
|
[Tool] Force inout port to be mandatory for I/O cells
|
2020-11-02 15:14:02 -07:00 |
|
tangxifan
|
e850dd5314
|
[Tool] Relax checking codes for embedded I/O circuit models
|
2020-11-02 13:54:31 -07:00 |
|
tangxifan
|
b78f8bec16
|
[Tool] Bug fixed for multi-region configuration frame
|
2020-10-30 21:19:20 -06:00 |
|
tangxifan
|
1e70825383
|
[OpenFPGA Tool] Add XML syntax for configurable regions
|
2020-09-28 13:51:43 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |
|
tangxifan
|
491433fae2
|
[OpenFPGA Tool] Update XML parser for fabric regions
|
2020-09-27 20:41:01 -06:00 |
|
tangxifan
|
48b2bff0d9
|
[OpenFPGA Tool] Update fabric key data structure to support regions
|
2020-09-27 20:08:11 -06:00 |
|
tangxifan
|
94047037c5
|
[OpenFPGA Tool] Streamline codes in openfpga arch parser
|
2020-09-27 14:33:14 -06:00 |
|
tangxifan
|
51d96244c6
|
[OpenFPGA Tool] Remove deprecated XML syntax
|
2020-09-26 14:30:57 -06:00 |
|
tangxifan
|
8b8ce22fd1
|
[OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library
|
2020-09-23 20:37:28 -06:00 |
|
tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
|
tangxifan
|
f284f6f8d0
|
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
|
tangxifan
|
8b6c8f73e9
|
[OpenFPGA code] fix bug for clang compatibility
|
2020-09-14 21:26:53 -06:00 |
|
tangxifan
|
c23742c751
|
[OpenFPGA code] fix bug for clang compatibility
|
2020-09-14 20:13:27 -06:00 |
|
tangxifan
|
fc6bfdc7a2
|
[OpenFPGA Code] Patch syntax compatibility for older gcc
|
2020-09-14 18:55:21 -06:00 |
|
tangxifan
|
c31d36deb6
|
[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
|
2020-09-14 16:16:03 -06:00 |
|
tangxifan
|
9c66a35bf6
|
[arch language] Now circuit library will automatically identify the default circuit model if needed
|
2020-08-23 14:06:03 -06:00 |
|
tangxifan
|
b83319bf14
|
[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
|
2020-08-23 13:48:22 -06:00 |
|
tangxifan
|
161d660837
|
update documentation for the initial offset when mapping physical pins
|
2020-08-19 15:00:46 -06:00 |
|
tangxifan
|
3eea12ceae
|
added a new XML syntax: initial offset for physical mode pin mapping
|
2020-08-19 14:43:44 -06:00 |
|
tangxifan
|
2712c354a9
|
now physical pb_port binding support multiple ports
|
2020-08-18 12:38:56 -06:00 |
|
tangxifan
|
35af0dd676
|
streamline fabric bitstream file format
|
2020-07-27 16:34:43 -06:00 |
|
tangxifan
|
92d2d2d849
|
add fabric bitstream XML writer
|
2020-07-26 21:00:57 -06:00 |
|
tangxifan
|
a3d22c56e3
|
bug fix in FPGA-SPICE
|
2020-07-24 19:51:32 -06:00 |
|
tangxifan
|
6d046efc52
|
add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
|
2020-07-24 16:25:27 -06:00 |
|
tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
|
tangxifan
|
de4586217f
|
now device binding is not mandatory for circuit models
|
2020-07-14 12:04:22 -06:00 |
|
tangxifan
|
e2b492f184
|
add circuit model tech binding
|
2020-07-13 20:35:10 -06:00 |
|
tangxifan
|
62fd0947f5
|
using a unified string to replace multi net names to save memory of bitstream database
|
2020-07-08 16:28:20 -06:00 |
|
tangxifan
|
824b56f14c
|
fabric key can now accept instance name only; decoders are no longer part of the key
|
2020-07-06 16:42:33 -06:00 |
|
tangxifan
|
1ad6e8292a
|
move constants from verilog domain to common so that FPGA-SPICE can share
|
2020-07-05 11:39:46 -06:00 |
|
tangxifan
|
2a9377b3f4
|
use encoded address in storage of fabric bitstream to save memory
|
2020-07-03 15:12:29 -06:00 |
|
tangxifan
|
70d9678578
|
reserve child block in bistream manager
|
2020-07-03 14:04:10 -06:00 |
|
tangxifan
|
7d9c36aae1
|
use length instead of msb in bitstream manager for block bits to save memory
|
2020-07-03 12:06:15 -06:00 |
|
tangxifan
|
2783fda344
|
use index range instead of vector for block bitstream
|
2020-07-03 11:42:38 -06:00 |
|
tangxifan
|
6ea857ae6c
|
use fast method to inquire number of bits and blocks in bitstream databases
|
2020-07-03 10:55:25 -06:00 |
|
tangxifan
|
6397cbe9d2
|
remove unused data in bitstream manager to compact memory usage
|
2020-07-03 10:35:35 -06:00 |
|
tangxifan
|
246b4d5ac6
|
reserve block bits to save memory
|
2020-07-02 21:52:32 -06:00 |
|
tangxifan
|
043fb54206
|
remove unused data in bitstream database
|
2020-07-02 20:53:18 -06:00 |
|
tangxifan
|
9799fea48f
|
optimizing bitstream storage
|
2020-07-02 19:33:53 -06:00 |
|
tangxifan
|
dee4be96af
|
reserve all the input/output net storage in bitstream manager
|
2020-07-02 19:17:34 -06:00 |
|
tangxifan
|
f97e3bfba6
|
add timer to openfpga shell
|
2020-07-02 18:02:33 -06:00 |
|
tangxifan
|
e82d0d9f34
|
drop id list in bitstream manager to save memory usage
|
2020-07-02 16:18:32 -06:00 |
|
tangxifan
|
9f19c36a89
|
use char in fabric bitstream to save memory footprint
|
2020-07-02 15:56:50 -06:00 |
|
tangxifan
|
405824081b
|
reserve configuration blocks and bits in bitstream manager builder to be memory efficient
|
2020-07-02 15:28:52 -06:00 |