tangxifan
|
77896379e2
|
[Arch] Add simulation setting for 8-clock architectures
|
2021-02-22 11:10:03 -07:00 |
|
tangxifan
|
16debe49f6
|
[Arch] Add more comments on the 4 clock simulation setting file
|
2021-02-22 11:04:34 -07:00 |
|
tangxifan
|
0ac75723af
|
[Arch] Add new architecture with 8 clocks
|
2021-02-22 11:00:45 -07:00 |
|
tangxifan
|
b9c2564a7e
|
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
|
2021-02-22 10:49:21 -07:00 |
|
tangxifan
|
bc8aa0ebc6
|
[Test] Remove routing test from quicklogic's flow test
|
2021-02-22 10:22:47 -07:00 |
|
tangxifan
|
2dbdc2644f
|
[Benchmark] Remove replicate micro benchmarks
|
2021-02-22 10:22:19 -07:00 |
|
tangxifan
|
9b6b2068ee
|
[Test] Move MCNC test to benchmark sweep test group
|
2021-02-22 10:18:34 -07:00 |
|
tangxifan
|
c1f4a434e4
|
[Doc] Update README for the regression test tasks
|
2021-02-22 10:17:02 -07:00 |
|
tangxifan
|
d6a02a985e
|
Merge pull request #248 from lnis-uofu/add_quicklogic_tests
Disabling verilog testbench generation for quicklogic tests
|
2021-02-22 09:02:29 -07:00 |
Lalit Sharma
|
d842026672
|
Disabling verilog testbench generation for quicklogic tests
|
2021-02-21 21:58:23 -08:00 |
Lalit Narain Sharma
|
be5e0cdea9
|
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
|
2021-02-22 09:50:26 +05:30 |
|
Lalit Sharma
|
576e6753f6
|
Removing 2 more tests which are variant of and design
|
2021-02-19 09:11:19 -08:00 |
|
Lalit Sharma
|
d4c5a5655a
|
Removing blif file as well as and2 testcase
|
2021-02-19 08:55:17 -08:00 |
|
Lalit Sharma
|
6de0954ca5
|
Uncommenting all benchmarks except 2 that requires multiple clocks
|
2021-02-19 08:40:26 -08:00 |
|
tangxifan
|
e08ac1a41e
|
[Test] Deploy synthesizable verilog test to CI
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
e19fc15fec
|
[Test] bug fix in test case
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
affc8cbbc4
|
[Test] Deploy test to CI
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
2e88b035ed
|
[Test] Add wire LUT repacker test case
|
2021-02-18 19:37:44 -07:00 |
|
tangxifan
|
1f097abe99
|
[Benchmark] Add micro benchmark for FIR filter
|
2021-02-18 19:37:44 -07:00 |
|
Lalit Sharma
|
69cdc11ea5
|
Uncommenting the tests that are running fine
|
2021-02-18 04:17:12 -08:00 |
|
tangxifan
|
d85d6e964e
|
Merge pull request #227 from watcag/master
Standard-cell flow
|
2021-02-17 10:11:34 -07:00 |
|
Lalit Sharma
|
7ee01711c2
|
Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
|
2021-02-17 00:06:59 -08:00 |
|
Lalit Sharma
|
44a979288b
|
Adding quicklogic tests and updating the corresponding conf file to run them
|
2021-02-16 23:08:38 -08:00 |
|
tangxifan
|
a819375f69
|
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
|
2021-02-16 16:53:13 -07:00 |
|
tangxifan
|
2c2e493739
|
[Test] Remove quicklogic test from basic tests
|
2021-02-16 12:29:10 -07:00 |
|
tangxifan
|
9c19e2b365
|
[Test] Move regression test scripts from workflow to openfpga_flow
|
2021-02-16 11:55:47 -07:00 |
Tarachand Pagarani
|
426b6449d8
|
change the test to turn off power analysis
|
2021-02-15 02:45:38 -08:00 |
|
Tarachand Pagarani
|
3a587f663a
|
copy yosys output file in case power analysis setting is off
|
2021-02-15 02:36:02 -08:00 |
|
tangxifan
|
e683e00032
|
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
|
2021-02-10 14:50:11 -07:00 |
|
tangxifan
|
9b86f3bb85
|
Merge branch 'master' into dev
|
2021-02-09 22:40:45 -07:00 |
|
tangxifan
|
22e675148e
|
[HDL] Add HDL codes for a super LUT with embedded carry logic
|
2021-02-09 21:13:22 -07:00 |
|
tangxifan
|
b81b74aa7c
|
[Arch] Patch architecture to support superLUT-related XML syntax
|
2021-02-09 20:23:32 -07:00 |
|
tangxifan
|
7dcc14d73f
|
[Arch] Bug fix in the example arch with super LUT
|
2021-02-09 15:52:22 -07:00 |
|
tangxifan
|
3ae501a5ea
|
[Test] Update test case to use dedicated eblif file
|
2021-02-09 15:51:57 -07:00 |
|
tangxifan
|
1712ee4edb
|
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
|
2021-02-09 15:41:21 -07:00 |
Nachiket Kapre
|
4c7f4bd82f
|
ahoy nice
|
2021-02-09 17:38:19 -05:00 |
|
tangxifan
|
2b51b36dd6
|
[Test] Now use the super LUT arch in the test case
|
2021-02-09 15:27:44 -07:00 |
|
tangxifan
|
56284059de
|
[Test] Add a test case for a super LUT
|
2021-02-09 15:25:32 -07:00 |
|
tangxifan
|
304b26c97f
|
[Arch] Add example architectures for superLUT circuit model
|
2021-02-09 15:11:12 -07:00 |
|
Nachiket Kapre
|
71c76df063
|
default to ns for time unit -- synopsys dc whines
|
2021-02-09 17:08:38 -05:00 |
|
Nachiket Kapre
|
6bb2e29f17
|
default to ns for time unit -- synopsys dc whines
|
2021-02-09 17:04:52 -05:00 |
|
Nachiket Kapre
|
87c69460df
|
what is going on
|
2021-02-09 11:33:08 -05:00 |
|
Nachiket Kapre
|
cc74c6268a
|
trying fix chan width
|
2021-02-09 11:28:19 -05:00 |
|
Nachiket Kapre
|
95fe4d7dae
|
adding dff synth
|
2021-02-09 10:34:54 -05:00 |
|
Nachiket Kapre
|
b14b5f975d
|
adding sweep for W
|
2021-02-09 08:48:25 -05:00 |
|
Nachiket Kapre
|
d7967da328
|
bugfix in alt
|
2021-02-08 23:04:00 -05:00 |
|
Nachiket Kapre
|
485708423c
|
no need for dff*, but need tap_buf4
|
2021-02-08 23:00:13 -05:00 |
|
Nachiket Kapre
|
cf154d8bb9
|
no need for dff*, but need tap_buf4
|
2021-02-08 22:29:55 -05:00 |
|
Nachiket Kapre
|
e14c0bf0c4
|
no need for dff*, but need tap_buf4
|
2021-02-08 22:28:42 -05:00 |
|
Nachiket Kapre
|
45437fbc46
|
no need for dff*, but need tap_buf4
|
2021-02-08 22:27:57 -05:00 |