tangxifan
|
76e03e3e14
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[core] code format
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2024-08-13 23:25:04 -07:00 |
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tangxifan
|
735adab9df
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[core] syntax due to clang
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2024-08-13 23:24:28 -07:00 |
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tangxifan
|
eb7639f44b
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[core] code format
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2024-08-13 22:37:34 -07:00 |
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tangxifan
|
812686d169
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[core] support global net fixup in pb pin fixup
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2024-08-13 22:36:37 -07:00 |
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tangxifan
|
ba5994a14c
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[core] more debugging messages
|
2024-08-13 21:03:49 -07:00 |
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tangxifan
|
c2d9696489
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[core] fixed a bug where some spines are not disabled
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2024-08-13 15:19:47 -07:00 |
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tangxifan
|
ad13058a0b
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[core] fixed a bug where unused last-level of clock spines are not disabled
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2024-08-13 15:04:13 -07:00 |
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tangxifan
|
4def678b11
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[core] code format
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2024-08-09 18:20:18 -07:00 |
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tangxifan
|
1af1306444
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[core] fixed a bug where pin index for subtile is wrongly calculated for clock network taps
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2024-08-09 18:02:49 -07:00 |
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tangxifan
|
f1ab44a212
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[core] fixed a bug
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2024-08-09 17:10:58 -07:00 |
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tangxifan
|
e4d7192e50
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[core] fixed a bug where subtile was used for clock network tap name
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2024-08-09 16:16:05 -07:00 |
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tangxifan
|
1d5acea7e0
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[core] typo
|
2024-08-06 20:17:15 -07:00 |
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tangxifan
|
1225679aac
|
[core] code format
|
2024-08-06 17:35:44 -07:00 |
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tangxifan
|
0dba4082d1
|
[core] syntax
|
2024-08-06 17:20:34 -07:00 |
|
tangxifan
|
ac2337d24b
|
[core] rework the option 'constant_undriven_inputs'
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2024-08-06 16:50:49 -07:00 |
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tangxifan
|
2e6b311d04
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[core] add more details to debug messages
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2024-08-02 18:33:43 -07:00 |
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tangxifan
|
eeaa3373c6
|
[core] code format
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2024-08-02 17:48:47 -07:00 |
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tangxifan
|
82cf7bbb8c
|
[core] Add verbose mode on find_node() for clock rr graph
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2024-08-02 17:47:41 -07:00 |
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tangxifan
|
1ec5847d5a
|
[core] typo
|
2024-08-02 14:27:43 -07:00 |
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tangxifan
|
f44c45bdd3
|
[core] code format
|
2024-08-02 14:23:35 -07:00 |
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tangxifan
|
f7e30b9974
|
[core] fixed a bug where pb pin fixup does not support perimeter cb
|
2024-08-02 14:21:22 -07:00 |
chungshien
|
b3c8c529d5
|
Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
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2024-07-31 12:25:37 -07:00 |
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tangxifan
|
d6db51f29e
|
[core] code format
|
2024-07-30 19:09:31 -07:00 |
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tangxifan
|
ef6b6f8e40
|
[core] remove warnings
|
2024-07-30 18:50:49 -07:00 |
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tangxifan
|
ae95357991
|
[core] code format
|
2024-07-30 15:40:41 -07:00 |
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tangxifan
|
a2c3af60d7
|
[core] fixed a bug where unique cb module is not considered as entry point
|
2024-07-30 15:39:44 -07:00 |
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tangxifan
|
853883cd36
|
[core] code format
|
2024-07-30 12:56:03 -07:00 |
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tangxifan
|
234eee19ae
|
[core] revert
|
2024-07-30 12:29:32 -07:00 |
chungshien-chai
|
0d9f1a3c6b
|
Forward searching the config bit + some minor refactor
|
2024-07-28 19:12:34 -07:00 |
|
chungshien-chai
|
2a3d69aded
|
Update code based on feedback
|
2024-07-28 02:37:15 -07:00 |
|
chungshien-chai
|
cbe9a46f95
|
Format and update doc
|
2024-07-28 00:02:20 -07:00 |
|
chungshien-chai
|
933155b08f
|
Update test flow
|
2024-07-27 23:52:54 -07:00 |
|
chungshien-chai
|
e60777d23e
|
Use Bitstream Setting XML
|
2024-07-26 01:36:49 -07:00 |
|
chungshien-chai
|
2ef362d53d
|
Init support overwriting bitstream
|
2024-07-25 17:40:46 -07:00 |
|
tangxifan
|
1513ea749b
|
[core] supporting clk spine on the same direction
|
2024-07-16 22:12:51 -07:00 |
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tangxifan
|
18d12109fb
|
[core] fixed a critical bug where cb port name using index is not considered on clock network entry
|
2024-07-16 17:42:21 -07:00 |
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tangxifan
|
c1f46c448a
|
[core] fixed a critical bug where clock network entry is on a CHANY
|
2024-07-16 17:04:44 -07:00 |
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tangxifan
|
cbd10e1222
|
[core] fixed a bug where tile module's global port is not derived from dedicated clock network
|
2024-07-16 16:58:21 -07:00 |
|
tangxifan
|
f607987386
|
[core] patch the out-of-range in clock rr nodes
|
2024-07-16 16:45:55 -07:00 |
|
tangxifan
|
c96f899c53
|
[core] code format
|
2024-07-10 15:07:26 -07:00 |
|
tangxifan
|
a4538fb25b
|
[core] now supports to_pin in building clock network for internal driver
|
2024-07-10 15:01:18 -07:00 |
|
tangxifan
|
215de8eb93
|
[core] code format
|
2024-07-10 14:17:22 -07:00 |
|
tangxifan
|
f5ba43e392
|
[core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench
|
2024-07-10 14:16:24 -07:00 |
|
tangxifan
|
213914e4ac
|
[core] code format
|
2024-07-10 12:23:57 -07:00 |
|
tangxifan
|
48e159dd8d
|
[core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches
|
2024-07-10 12:23:15 -07:00 |
|
tangxifan
|
c6dd33a965
|
[core] fixed a bug when annotating global nets on OPIN
|
2024-07-10 11:59:25 -07:00 |
|
tangxifan
|
96bdcc8b35
|
[core] code format
|
2024-07-09 22:54:55 -07:00 |
|
tangxifan
|
27e29f949c
|
[core] fixed a bug where the pin idx of global net on rr graph is not well annotated
|
2024-07-09 22:53:12 -07:00 |
|
tangxifan
|
092b8b038f
|
[core] remove verbose out
|
2024-07-08 22:23:37 -07:00 |
|
tangxifan
|
04504e4d5d
|
[core] code format
|
2024-07-08 22:22:59 -07:00 |