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[core] fixed a bug where pb pin fixup does not support perimeter cb

This commit is contained in:
tangxifan 2024-08-02 14:21:22 -07:00
parent ad38b52a23
commit f7e30b9974
3 changed files with 20 additions and 5 deletions
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20
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -36,7 +36,9 @@ static void update_cluster_pin_with_post_routing_results(
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer,
const vtr::Point<size_t>& grid_coord, const ClusterBlockId& blk_id,
const e_side& border_side, const size_t& z, const bool& verbose) {
const e_side& border_side, const size_t& z,
const bool& perimeter_cb,
const bool& verbose) {
/* Handle each pin */
auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
auto physical_tile = device_ctx.grid.get_physical_type(
@ -76,6 +78,13 @@ static void update_cluster_pin_with_post_routing_results(
if (NUM_SIDES == border_side) {
VTR_ASSERT(1 == pin_sides.size());
pin_side = pin_sides[0];
} else if (perimeter_cb) {
/* When perimeter connection blcoks are allowed, I/O pins may occur on any side but the border side */
VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(),
pin_sides.end(),
border_side));
VTR_ASSERT(1 == pin_sides.size());
pin_side = pin_sides[0];
} else {
SideManager side_manager(border_side);
VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(),
@ -188,7 +197,9 @@ void update_pb_pin_with_post_routing_results(
const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
const PlacementContext& placement_ctx,
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose) {
VprClusteringAnnotation& vpr_clustering_annotation,
const bool& perimeter_cb,
const bool& verbose) {
/* Ensure a clean start: remove all the remapping results from VTR's
* post-routing clustering result sync-up */
vpr_clustering_annotation.clear_net_remapping();
@ -219,7 +230,7 @@ void update_pb_pin_with_post_routing_results(
device_ctx, clustering_ctx, vpr_routing_annotation,
vpr_clustering_annotation, layer, grid_coord, cluster_blk_id,
NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile,
verbose);
perimeter_cb, verbose);
}
}
}
@ -250,7 +261,8 @@ void update_pb_pin_with_post_routing_results(
update_cluster_pin_with_post_routing_results(
device_ctx, clustering_ctx, vpr_routing_annotation,
vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side,
placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, verbose);
placement_ctx.block_locs[cluster_blk_id].loc.sub_tile,
perimeter_cb, verbose);
}
}
}

4
openfpga/src/base/openfpga_pb_pin_fixup.h
View File

@ -18,7 +18,9 @@ void update_pb_pin_with_post_routing_results(
const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
const PlacementContext& placement_ctx,
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose);
VprClusteringAnnotation& vpr_clustering_annotation,
const bool& perimeter_cb,
const bool& verbose);
} /* end namespace openfpga */

1
openfpga/src/base/openfpga_pb_pin_fixup_template.h
View File

@ -42,6 +42,7 @@ int pb_pin_fixup_template(T& openfpga_context, const Command& cmd,
g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.placement(),
openfpga_context.vpr_routing_annotation(),
openfpga_context.mutable_vpr_clustering_annotation(),
g_vpr_ctx.device().arch->perimeter_cb,
cmd_context.option_enable(cmd, opt_verbose));
/* TODO: should identify the error code from internal function execution */