riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] fixed a bug where subtile was used for clock network tap name

This commit is contained in:
tangxifan 2024-08-09 16:16:05 -07:00
parent a4091efc79
commit e4d7192e50
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -152,6 +152,10 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
pin_name.c_str(), physical_tile->capacity - 1);
exit(1);
}
/* Bypass unmatched subtiles*/
if (tile_info.get_name() != std::string(physical_tile->name)) {
return pin_idx;
}
/* precheck: return unfound pin if the subtile index does not match */
if (tile_info.get_width() != 1) {
VTR_LOG_ERROR(
@ -175,9 +179,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
/* Spot the subtile by using the index */
for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
/* Bypass unmatched subtiles*/
if (tile_info.get_name() != std::string(sub_tile.name)) {
continue;
}
if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) {
VTR_LOG_ERROR(
"Invalid pin name '%s' whose subtile index is out of range, expect "