From e4d7192e505ae960c0df18fccca56c6232649f3a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Aug 2024 16:16:05 -0700 Subject: [PATCH] [core] fixed a bug where subtile was used for clock network tap name --- openfpga/src/utils/openfpga_physical_tile_utils.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index fd77cc072..3a583cd73 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -152,6 +152,10 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, pin_name.c_str(), physical_tile->capacity - 1); exit(1); } + /* Bypass unmatched subtiles*/ + if (tile_info.get_name() != std::string(physical_tile->name)) { + return pin_idx; + } /* precheck: return unfound pin if the subtile index does not match */ if (tile_info.get_width() != 1) { VTR_LOG_ERROR( @@ -175,9 +179,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, /* Spot the subtile by using the index */ for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { /* Bypass unmatched subtiles*/ - if (tile_info.get_name() != std::string(sub_tile.name)) { - continue; - } if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) { VTR_LOG_ERROR( "Invalid pin name '%s' whose subtile index is out of range, expect "