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[core] typo

This commit is contained in:
tangxifan 2024-08-06 20:17:15 -07:00
parent 1225679aac
commit 1d5acea7e0
1 changed files with 1 additions and 1 deletions
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openfpga/src/base/openfpga_verilog_command_template.h
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@ -32,7 +32,7 @@ ShellCommandId add_write_fabric_verilog_command_template(
/* Add an option '--constant_undriven_inputs' */
CommandOptionId const_undriven_inputs_opt = shell_cmd.add_option(
"constant_undriven_inputs", true,
"constant_undriven_inputs", false,
"Can be [none|bus0|bus1|bit0|bit1]. Use constant vdd/gnd for undriven "
"wires in Verilog netlists. Recommand to "
"enable when there are boundary routing tracks in FPGA fabric");