From 1d5acea7e0477a5c326a648db67dc2a010e839be Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Aug 2024 20:17:15 -0700 Subject: [PATCH] [core] typo --- openfpga/src/base/openfpga_verilog_command_template.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h index 4e2efe0e8..99376f5fe 100644 --- a/openfpga/src/base/openfpga_verilog_command_template.h +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -32,7 +32,7 @@ ShellCommandId add_write_fabric_verilog_command_template( /* Add an option '--constant_undriven_inputs' */ CommandOptionId const_undriven_inputs_opt = shell_cmd.add_option( - "constant_undriven_inputs", true, + "constant_undriven_inputs", false, "Can be [none|bus0|bus1|bit0|bit1]. Use constant vdd/gnd for undriven " "wires in Verilog netlists. Recommand to " "enable when there are boundary routing tracks in FPGA fabric");