riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] fixed a bug where pin index for subtile is wrongly calculated for clock network taps

This commit is contained in:
tangxifan 2024-08-09 18:02:49 -07:00
parent f1ab44a212
commit 1af1306444
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -177,9 +177,11 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
}
/* Spot the subtile by using the index */
size_t acc_pin_index = 0;
for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
/* Bypass unmatched subtiles*/
if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) {
acc_pin_index += sub_tile.num_phy_pins;
continue;
}
for (const t_physical_tile_port& sub_tile_port : sub_tile.ports) {
@ -202,6 +204,7 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
}
/* Reach here, we get the port we want, return the accumulated index */
size_t accumulated_pin_idx =
acc_pin_index +
sub_tile_port.absolute_first_pin_index +
(sub_tile.num_phy_pins / sub_tile.capacity.total()) *
(tile_info.get_lsb() - sub_tile.capacity.low) +