From 1af130644433419c7168cda4163cf7f320f8e454 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 9 Aug 2024 18:02:49 -0700
Subject: [PATCH] [core] fixed a bug where pin index for subtile is wrongly
 calculated for clock network taps

---
 openfpga/src/utils/openfpga_physical_tile_utils.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp
index 4cab47c90..dd9cf1fc5 100644
--- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp
+++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp
@@ -177,9 +177,11 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
   }
 
   /* Spot the subtile by using the index */
+  size_t acc_pin_index = 0;
   for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
     /* Bypass unmatched subtiles*/
     if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) {
+      acc_pin_index += sub_tile.num_phy_pins;
       continue;
     }
     for (const t_physical_tile_port& sub_tile_port : sub_tile.ports) {
@@ -202,6 +204,7 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
       }
       /* Reach here, we get the port we want, return the accumulated index */
       size_t accumulated_pin_idx =
+        acc_pin_index +
         sub_tile_port.absolute_first_pin_index +
         (sub_tile.num_phy_pins / sub_tile.capacity.total()) *
           (tile_info.get_lsb() - sub_tile.capacity.low) +