Commit Graph

959 Commits

Author SHA1 Message Date
AurelienUoU 640922accd Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-27 16:54:13 -06:00
AurelienUoU a93d7e57f7 Scan chain support in directlist 2019-09-27 16:53:00 -06:00
tangxifan 167778cf57 refactoring MUX Verilog instanciation in Switch block 2019-09-27 16:05:47 -06:00
tangxifan dbe1625267 Refactored Verilog wiring for formal verification ports in Switch Blocks 2019-09-27 13:51:22 -06:00
tangxifan ead014e7d8 refactoring the configuration bus Verilog generation for MUXes 2019-09-27 11:47:34 -06:00
tangxifan 091bbd4d9c start refactoring the num_config_bits for circuit model 2019-09-26 22:53:07 -06:00
tangxifan 8ccf681749 Merge branch 'dev' into refactoring 2019-09-26 21:00:19 -06:00
tangxifan f0589cc2cf refactoring mux Verilog generation for switch blocks 2019-09-26 20:59:19 -06:00
tangxifan 05eaa412b1 refactored short-connection of switch block 2019-09-26 14:31:05 -06:00
AurelienUoU 3b13c959f3 Finish renaming SCFF to CCFF 2019-09-26 14:04:40 -06:00
AurelienUoU c4449b667f Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-26 11:34:59 -06:00
AurelienUoU 056219f180 Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
tangxifan ea0da49e04 Merge branch 'dev' into refactoring 2019-09-25 21:06:06 -06:00
tangxifan 5bb40e7f74 refactored local wire generation for Switch block 2019-09-25 21:05:02 -06:00
AurelienUoU e5faeb1400 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-25 16:50:53 -06:00
AurelienUoU a35e2936b2 Fix verilog generation for direct connexion from directlist 2019-09-25 16:44:00 -06:00
tangxifan 2b0e2615fa refactored sram port addition to module manager 2019-09-25 16:09:58 -06:00
tangxifan c911f15a67 add formal verification port to SB Verilog generation 2019-09-23 21:15:45 -06:00
tangxifan e1742b68ef add pre-processing flag support for module manager 2019-09-23 20:25:53 -06:00
AurelienUoU feddcbcb21 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-23 11:41:38 -06:00
tangxifan d2ddbc19a3 refactoring the reserved sram port generation 2019-09-22 16:38:16 -06:00
tangxifan 8b3de892ef simplify the regression test commands 2019-09-22 12:18:44 -06:00
tangxifan 2c4372c506 add reserved BLB/WL port naming 2019-09-22 12:16:43 -06:00
tangxifan 1e4177067d remove port size in the module definition 2019-09-22 11:21:43 -06:00
tangxifan 5efea159c5 Simplify part of regression test to min_route_chan_width 2019-09-22 11:14:33 -06:00
Ganesh Gore 1dffe54807 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-22 00:21:25 -06:00
Ganesh Gore 50039a4b6e Added remove run directory option 2019-09-21 23:35:56 -06:00
AurelienUoU cc0bfdd548 Add testcase in regression test for architecture with 1 IO cell/IO block 2019-09-20 10:27:26 -06:00
tangxifan 0ff0c8cf06 bug fix for IO=1 2019-09-19 15:43:25 -06:00
tangxifan 4e7af5cdc5 update tileable_routing test 2019-09-18 15:59:32 -06:00
tangxifan e0b253d30a minor fix for non-LUT intermedate buffer case 2019-09-18 15:15:03 -06:00
tangxifan 0f0d06aad7 add non-LUT intermediate buffer to test and apply minor bug fix 2019-09-18 15:04:51 -06:00
Ganesh Gore 8afcba2c45 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-18 12:15:42 -06:00
Ganesh Gore cd5fd6ce6c Added explicit checking to VVP execution 2019-09-18 12:14:26 -06:00
Ganesh Gore 56c40ca06d Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-17 22:12:11 -06:00
Ganesh Gore 169732ccc1 Added verbose option in VVP output 2019-09-17 22:09:37 -06:00
tangxifan d7ac7d3649 start refactoring the switch block verilog generation 2019-09-17 20:40:26 -06:00
Ganesh Gore 7be83235a0 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-16 21:25:26 -06:00
Ganesh Gore 678e3181ba Made compact_routing_hierarchy options uncond 2019-09-16 21:22:13 -06:00
tangxifan 5abbfd6a0f add tileable routing to regression test 2019-09-16 20:45:02 -06:00
tangxifan 2294aecef2 remove old codes and compact new codes 2019-09-16 20:19:14 -06:00
tangxifan c5ee81541a remove dead codes in routing module generation 2019-09-16 18:47:01 -06:00
tangxifan 0963852091 remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
2019-09-16 18:38:37 -06:00
tangxifan d83cad7c2e refactoring Verilog generation for routing channels 2019-09-16 17:35:51 -06:00
Ganesh Gore 81b9c5b266 Added flag for VVP exit code 2019-09-14 12:35:47 -06:00
Ganesh Gore d90329678a Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-09-14 12:11:36 -06:00
Ganesh Gore ec3854a648 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-14 00:14:17 -06:00
Ganesh Gore e5c99c8b12 Quick terminate on fail added 2019-09-13 23:56:38 -06:00
Ganesh Gore 10eba0f78c Updated script.sh with new paramters 2019-09-13 23:31:23 -06:00
Ganesh Gore bd9e57bc37 Added better task name 2019-09-13 23:30:42 -06:00