df23daf026
[lib] sanity check on global port name and from pin name of tap points
2024-07-01 17:37:16 -07:00
7c487eadc9
[core] now clock network keep port info in a native data structure
2024-07-01 16:58:23 -07:00
3afb92d6a5
[core] code format
2024-06-30 22:48:15 -07:00
1fd974d544
[core] fixed a bug where clock network size cannot impact global port on top module
2024-06-29 17:35:47 -07:00
34fb003911
[core] replace width syntax with global port name
2024-06-29 10:46:00 -07:00
5cfd23747b
[core] code format
2024-06-28 13:47:03 -07:00
4185235a69
[core] now clock routing is based on tree expansion. Unused part can be disconnected
2024-06-27 15:02:20 -07:00
cab649893b
[core] update clock architecture
2024-06-26 18:06:39 -07:00
59be95b227
[core] code format
2024-06-26 17:58:26 -07:00
3efa97b84e
[core] support coordinate on clock taps
2024-06-26 17:40:11 -07:00
3b25e42720
[lib] syntax
2024-06-26 15:51:00 -07:00
381a8cb535
[lib] clock tap syntax are reworked. Support region, single, all and from/to ports
2024-06-26 15:41:56 -07:00
4640e74e7e
[core] code format
2024-06-25 12:25:16 -07:00
66af73e91e
[lib] now accept reset and set in programmable clock network
2024-06-25 12:24:46 -07:00
7bcbd8a88b
[core] code format
2024-06-25 11:44:50 -07:00
3b2c13402a
[core] syntax
2024-06-25 11:44:25 -07:00
31d4b4c402
[core] now support add internal drivers to clock tree
2024-06-25 11:27:22 -07:00
272d78eb43
[test] add a new unit test
2024-06-24 19:13:36 -07:00
22bee35fd1
[lib] mem allocate
2024-06-24 18:47:56 -07:00
36ef555dda
[lib] add example arch for clock arch with internal drivers
2024-06-24 18:33:47 -07:00
2eda2825b7
[lib] syntax
2024-06-24 18:28:42 -07:00
0c442f6238
[lib] add syntax to support internal drivers in clock network parsers
2024-06-24 17:54:58 -07:00
2193f108ee
[core] add debugging messages
2024-06-21 18:42:35 -07:00
ecd31955b1
[core] code format
2024-06-21 17:11:32 -07:00
3ddaefc2a2
[lib] syntax
2024-06-21 17:02:37 -07:00
1ab75cf76c
[lib] now link clock arch supports tap and driver default switches
2024-06-21 16:52:22 -07:00
9ccd14bf4d
[lib] now default switch of clk ntwk is split to default_tap_switch and default_driver_switch
2024-06-21 16:45:05 -07:00
ca6e2f9831
[core] code format
2024-05-20 13:41:35 -07:00
b15e169490
[core] fixed a bug where wire model is expected on direct connections
2024-05-20 12:45:49 -07:00
9d87e99539
[lib] typo on keywords in XML parser
2024-05-20 11:15:43 -07:00
926b9e9739
[core] code format
2024-05-18 12:33:19 -07:00
3b93bea3d1
[core] syntax
2024-05-18 12:29:38 -07:00
be1d7517c9
[doc] rework out-of-date syntax
2024-05-17 19:25:35 -07:00
0d8c21ca84
[core] add new type 'part_of_cb' for tile direct connections
2024-05-17 18:59:53 -07:00
36d37289fe
[lib] add missing header required by clang-11+
2024-05-05 21:21:36 -07:00
03bea1c566
[lib] code format
2024-05-05 18:47:37 -07:00
df3b4357fc
[lib] add header to pass Gcc-12
2024-05-05 18:24:44 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
135dbb783c
reformat the code
2024-03-06 20:03:58 -08:00
4e77551479
bypass error
2024-03-06 00:56:21 -08:00
0b4bdd752d
reformat the code
2024-03-05 22:34:00 -08:00
c127d29262
disable error message for specific commands
2024-03-05 22:29:57 -08:00
39a012b939
Support checking illegal pin constraint (use loc as key and update message format)
2024-03-04 12:41:19 +08:00
d2a8213566
Support checking illegal pin constraint (optimize and add comments)
2024-02-28 11:23:03 +08:00
f4658ee67d
Support checking illegal pin constraint (Show design pins)
2024-02-27 16:50:00 +08:00
3138481df4
Support checking illegal pin constraint
2024-02-27 10:21:16 +08:00
1d0d8c5417
Update read_xml_repack_design_constraints.cpp
...
code clean up
2023-12-05 10:13:53 -08:00
e6c9d22ce9
Update repack_design_constraints.h
...
code clean up
2023-12-05 10:10:19 -08:00
aa51b6d388
Update repack_design_constraints.h
2023-12-05 09:40:25 -08:00
57f3b7af0f
Update repack_design_constraints.h
2023-12-05 09:38:27 -08:00
b765410300
Update repack_design_constraints.cpp
2023-12-05 09:37:56 -08:00
7aa882f82c
Update read_xml_repack_design_constraints.cpp
2023-12-05 09:26:05 -08:00
0e243d1c05
Update repack_design_constraints.cpp
2023-12-05 09:17:29 -08:00
d0958fc017
Update repack_design_constraints.h
2023-12-05 09:09:45 -08:00
a50b007d72
add vtr assert
2023-12-01 03:02:52 -08:00
539d41f3df
reformat the code
2023-11-29 17:42:13 -08:00
2511b79bd6
format the code
2023-11-29 02:27:53 -08:00
030f9d8837
changes according to code review
2023-11-29 02:12:07 -08:00
d28f024b61
minor change
2023-11-29 01:53:18 -08:00
1aac6681bc
Merge branch 'master' into repack_debug
2023-11-22 10:48:59 -08:00
ee392f1b46
add ignore_net to repackdesign constraint
2023-11-21 21:47:03 -08:00
93cbbf2045
[core] code format
2023-10-06 18:20:55 -07:00
b07111497c
[core] enable options in xml writers
2023-10-06 18:20:17 -07:00
76f446caec
[core] fixed a bug
2023-09-25 21:13:11 -07:00
3adf81046a
[core] code format
2023-09-25 17:22:26 -07:00
5e269e8bc4
[core] support port merging at grid modules
2023-09-25 17:21:58 -07:00
fd99dafad7
[core] code format
2023-09-25 16:51:01 -07:00
96f36a96dd
[core] syntax
2023-09-25 16:50:30 -07:00
ca715f4c82
[core] developing parser to support subtile port merge
2023-09-25 16:46:34 -07:00
0a94763422
[lib] add module rename assistant
2023-09-22 18:16:01 -07:00
278b8e2409
[lib] fixed a typo which causes outputted module name XMLs carry syntax errors
2023-09-22 17:37:27 -07:00
c6175aa514
[core] code format
2023-09-17 22:37:48 -07:00
ef97127c63
[core] fixed some bugs in testbenches when renaming top modules
2023-09-17 22:34:00 -07:00
72a3c05747
[core] code format
2023-09-17 13:29:30 -07:00
ccd4c1861b
[core] developing new command to write module naming rules
2023-09-16 19:37:06 -07:00
37573abc22
[core] code format
2023-09-15 23:32:40 -07:00
bc407e5d69
[core] code complete for rename modules
2023-09-15 23:22:31 -07:00
7913e6cc6a
[lib] update tests and fixed some bugs
2023-09-15 17:38:51 -07:00
b5cf08a3c5
[lib] add testing
2023-09-15 17:15:05 -07:00
74b9f673ec
[lib] syntax and add missing api
2023-09-15 17:00:02 -07:00
636647902e
[lib] developing io for module name map
2023-09-15 16:53:24 -07:00
e5bc936144
[lib] developing io
2023-09-15 16:19:10 -07:00
b65dda90c4
[lib] developing naming manager
2023-09-15 16:02:13 -07:00
af67b02cca
[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
2023-09-15 13:51:14 -07:00
3273728bc3
[lib] code format
2023-08-26 18:15:30 -07:00
ac5873bac2
[lib] fixed some bugs in message show
2023-08-26 18:12:25 -07:00
97619fc545
[lib] add verbose output option to fabric key assistant
2023-08-26 18:07:08 -07:00
cfaae55bda
[lib] debugged fabric key assistant
2023-08-26 13:19:18 -07:00
adae7392e5
[lib] developing fabric key assistant
2023-08-26 12:54:12 -07:00
d3895c3dc0
[core] code format
2023-08-03 17:34:25 -07:00
53050b94ab
[core] developing memory group modules in grid modules
2023-08-01 17:50:03 -07:00
23643f3fb1
[core] developing the physical memory block builder
2023-07-31 22:57:26 -07:00
95a32628ab
[core] fixed the bug in arch bitgen due to the tile modules
2023-07-25 14:15:15 -07:00
7783229d90
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_fabric_tile
2023-07-23 20:44:50 -07:00
6607bb7e48
[core] now fpga verilog supports tile modules
2023-07-18 22:35:22 -07:00
b2f5b493c2
Fix the cpp-format
2023-07-16 13:08:40 -07:00
924622f5e5
Issue 1248 - fix bug bintoi_charvec()
2023-07-15 17:46:43 -07:00
091ac88c7e
[lib] code format
2023-07-14 12:16:40 -07:00
3bc959dcec
[lib] create tile config lib and start integration to core
2023-07-14 12:13:31 -07:00
tangxifan
chungshien
ubuntu
Victor
Yitian4Debug
Chung Shien Chai