tangxifan
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571a012724
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[test] xml format
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2023-03-07 18:47:55 -08:00 |
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tangxifan
|
7e3b656c51
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[test] fixed a bug in arch
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2023-03-06 23:06:32 -08:00 |
|
tangxifan
|
fd1c4039d3
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[test] typo
|
2023-03-02 21:37:24 -08:00 |
|
tangxifan
|
02b50e3464
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[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
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2023-03-02 21:33:32 -08:00 |
|
tangxifan
|
b9f7c72a96
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[test] fixed some bugs in arch
|
2023-03-02 18:16:59 -08:00 |
|
tangxifan
|
5917446fbe
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[arch] code format
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2023-02-28 22:01:49 -08:00 |
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tangxifan
|
780dec6b1b
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[test] add a new test to validate the programmable clock arch
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2023-02-28 21:46:57 -08:00 |
Ganesh Gore
|
4f6b8c0905
|
Updated regression tests
|
2023-02-11 22:11:06 -07:00 |
|
Ganesh Gore
|
f7c710e95e
|
renamed yosys_vpr_template fabric_netlist_gen_template
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2023-02-11 18:33:06 -07:00 |
|
Ganesh Gore
|
b2bdfb7475
|
Strip down task
|
2023-02-11 18:32:06 -07:00 |
|
Ganesh Gore
|
b71a1014e8
|
renamed vpr_blif_template to fabric_verification_template
|
2023-02-11 18:29:21 -07:00 |
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Ganesh Gore
|
6a48f1eb05
|
Updated demo projects
|
2023-02-11 18:24:20 -07:00 |
|
Ganesh Gore
|
a6263c44af
|
Updated format
|
2023-02-11 18:12:04 -07:00 |
|
Ganesh Gore
|
2afb91596f
|
Refactored run_openfpga_task.py
|
2023-02-11 18:04:54 -07:00 |
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tangxifan
|
57cec96d7e
|
[script] wrong path to yosys bin
|
2023-02-03 22:54:22 -08:00 |
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tangxifan
|
ff31a7b828
|
[script] fixed the path to yosys bin for openfpga flow
|
2023-02-03 22:12:03 -08:00 |
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tangxifan
|
aff8178581
|
[test] fixed remaining bugs
|
2023-01-24 18:00:04 -08:00 |
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tangxifan
|
d1e951e52e
|
[test] debugging
|
2023-01-24 17:57:34 -08:00 |
|
tangxifan
|
f964c9ed67
|
[test] debug
|
2023-01-24 15:48:57 -08:00 |
|
tangxifan
|
8174f53796
|
[test] deploy new test to fpga bitstream regression
|
2023-01-24 15:42:01 -08:00 |
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tangxifan
|
499d352cff
|
[flow] add yosys rewrite scripts
|
2023-01-24 15:39:42 -08:00 |
|
tangxifan
|
e7a3b48475
|
[arch] comment on the wrong mode bits
|
2023-01-24 15:24:17 -08:00 |
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tangxifan
|
fec84d76d1
|
[arch] adding tech lib;
|
2023-01-24 15:22:34 -08:00 |
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tangxifan
|
1d8c1a6803
|
[arch] adding a new arch to validate fracturable dsp
|
2023-01-24 15:17:50 -08:00 |
|
tangxifan
|
d60d0540da
|
[test] adding a new test case to validate the bitstream overloading for DSP blocks
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2023-01-24 14:58:52 -08:00 |
|
tangxifan
|
f586229b97
|
[test] enable rst_on_lut benchmark
|
2023-01-18 19:45:41 -08:00 |
|
tangxifan
|
b7a66705e0
|
[test] now use yosys_vpr flow; add rst_on_lut benchmark
|
2023-01-18 19:42:50 -08:00 |
|
tangxifan
|
bc51be4863
|
[benchmark] syntax
|
2023-01-18 18:34:24 -08:00 |
|
tangxifan
|
e974e5ddf7
|
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
|
2023-01-18 18:31:36 -08:00 |
|
tangxifan
|
acc905fa11
|
[arch] add support to route reset to LUTs
|
2023-01-18 18:22:37 -08:00 |
|
tangxifan
|
95dd4fd535
|
[test] deploy new test to basic regression tests
|
2023-01-18 18:17:53 -08:00 |
|
tangxifan
|
03273371c0
|
[test] add a new test to validate local reset
|
2023-01-18 18:17:14 -08:00 |
|
tangxifan
|
c9e00b7abc
|
[arch] add a new example arch that supports local reset
|
2023-01-18 18:05:52 -08:00 |
|
tangxifan
|
b6ae829518
|
[benchmark] add a new benchmark to validate dff
|
2023-01-18 17:59:52 -08:00 |
|
tangxifan
|
2c9593c1d4
|
[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
|
2023-01-15 13:09:40 -08:00 |
|
tangxifan
|
13aed6fff5
|
[test] still commment verification out
|
2023-01-15 12:17:59 -08:00 |
|
tangxifan
|
758cc7a089
|
[test] debugging
|
2023-01-15 11:44:48 -08:00 |
|
tangxifan
|
14bb76ec87
|
[test] remove verification steps for new test but leave a todo
|
2023-01-14 23:06:54 -08:00 |
|
tangxifan
|
297092f1fe
|
[arch] now use a local clock as an input of a CLB
|
2023-01-14 22:12:00 -08:00 |
|
tangxifan
|
5aa85d82e6
|
[test] deploy the new test to basic regression tests
|
2023-01-13 22:07:45 -08:00 |
|
tangxifan
|
9222d085cd
|
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
|
2023-01-13 22:04:56 -08:00 |
|
tangxifan
|
26f71656de
|
[test] update pin constraints
|
2023-01-13 21:12:18 -08:00 |
|
tangxifan
|
9e462d96e0
|
[arch] now use a dedicated input for locally generated clock signals
|
2023-01-13 20:46:04 -08:00 |
|
tangxifan
|
93107c752a
|
[test] updating test case
|
2023-01-13 19:53:15 -08:00 |
|
tangxifan
|
1fb39f803b
|
[doc] updated vpr arch naming rules
|
2023-01-13 19:52:58 -08:00 |
|
tangxifan
|
a06ee30ca0
|
[arch] added a new vpr arch where clock can be generated by internal logics
|
2023-01-13 19:35:00 -08:00 |
|
tangxifan
|
1353577351
|
[test] added a new test to validate locally generated clocks
|
2023-01-13 16:45:30 -08:00 |
|
tangxifan
|
6400605603
|
[benchmark] add clock divider
|
2023-01-13 16:39:06 -08:00 |
|
tangxifan
|
bbf83101be
|
[test] deploy new test to ci
|
2023-01-11 17:11:28 -08:00 |
|
tangxifan
|
c7dc3ce7dc
|
[test] pass
|
2023-01-11 17:10:29 -08:00 |