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OpenFPGA
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280 Commits 70 Branches 8 Tags 105 MiB
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78 Commits

Author SHA1 Message Date
tangxifan 4c6639218e Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-08 14:30:33 -06:00
tangxifan e305e60ee4 minor fix on the shell interface of VPR 2019-05-08 14:29:58 -06:00
Baudouin Chauviere 4f386de2ef gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere 2019-05-06 17:25:29 -06:00
Baudouin Chauviere 7ddfe60721 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-06 16:12:52 -06:00
Baudouin Chauviere 3b62f8e024 Conversion from s to ns for the loop breaking delays 2019-05-06 16:12:30 -06:00
BaudouinChauviere cd4dc8b2e8
Delete read_xml_arch_file.c 
Already present in SRC
 2019-05-06 12:55:18 -06:00
Baudouin Chauviere a5a1a376ab Modified code for cleaner delay naming convention 2019-05-06 12:52:49 -06:00
Baudouin Chauviere e7b1d89985 Change syntax name for loop_breaker_delay_before/after which is more explicit 2019-05-06 12:25:26 -06:00
Baudouin Chauviere 7c257ebda7 Fix on the makefile which was not targetting the right folder 2019-05-06 12:21:53 -06:00
tangxifan 6e6ae1cc3d fixed bugs in CMakeLists.txt and Makefile 2019-05-03 23:03:04 -06:00
tangxifan 4e3487b691 Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
tangxifan 70b66e0799 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-03 14:22:20 -06:00
Baudouin Chauviere 7860042276 added before after loop breaker constraining 2019-05-03 14:00:06 -06:00
tangxifan 11cf30b239 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-03 11:54:35 -06:00
tangxifan 5a97e3e602 update Makefile t 2019-05-03 11:48:41 -06:00
Baudouin Chauviere 4e330ee463 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-03 10:43:22 -06:00
Baudouin Chauviere 921b694400 Bug fix sdc breaking loop of edges outside current interconnect 2019-05-03 10:42:35 -06:00
AurelienUoU 42f20eda60 Add the user matching for internal register in formal verification script generation 2019-05-03 10:24:02 -06:00
tangxifan 974af5a2ae Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-04-30 14:30:38 -06:00
tangxifan 42daadee2f critical bug fixing 2019-04-30 14:30:17 -06:00
Baudouin Chauviere 1ab4688339 Create no segment constraint in loop_breaker if none is given by user 2019-04-30 12:30:07 -06:00
tangxifan c46c0fc97d bug fixing for SDC generator 2019-04-26 14:07:44 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
tangxifan 8eeb144f32 Streamline Makefile and Travis for Mac OS 2019-04-10 15:22:20 +08:00
Baudouin Chauviere c4b42726c4 fixes easing thehandling by the user. 2019-03-31 07:55:05 -06:00
tangxifan b06df18a89
Update rr_graph_area.c 2019-03-11 21:46:42 +08:00
AurelienUoU 213f94ddee Correct preconfiguration 2019-01-31 16:43:47 -07:00
tangxifan 5e36aa82c5 fixa bug in determining mux structure 2019-01-22 13:54:50 -07:00
Baudouin Chauviere f3e7ae0823 Hot fix 2019-01-10 17:37:15 -07:00
tangxifan b8187bbca5 fix a bug for supporting default circuit_model of LUTs and FFs 2019-01-10 15:10:05 -07:00
Baudouin Chauviere 4ae3aa517c go.sh replaces the paths now 2019-01-09 23:16:43 -07:00
Baudouin Chauviere 510c27f816 Removed commercial scripts, replaced by academia ones 2019-01-09 11:56:07 -07:00
Baudouin Chauviere 3b4fc16c60 Adding help message on the go.sh 2019-01-09 11:54:28 -07:00
tangxifan 66701838ff update relative path in ARCH XML 2019-01-08 11:41:24 -07:00
AurelienUoU b80e435548 Correct manual testbench generation bug 2019-01-07 18:03:56 -07:00
AurelienUoU 7ff245448b Add new benchmark and modify go.sh to use it 2018-12-26 04:24:26 -07:00
AurelienUoU 21dc8a006f Change simulator script generation (waves) 2018-12-14 14:40:04 -07:00
tangxifan ee6b1d6cd6 adapt arch xml and act for demo 2018-12-13 22:46:40 -07:00
tangxifan 3d9e913e4e add a benchmark fifo 2018-12-12 16:45:33 -07:00
AurelienUoU cc5a01d476 Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
AurelienUoU a70b0ac9ac Correct go.sh 2018-12-11 15:51:21 -07:00
AurelienUoU 317c3b59c9 Update go.sh and upload pip_add.v 2018-12-11 15:47:05 -07:00
AurelienUoU fb0992bd85 Update go.sh and Makefile 2018-12-11 15:31:32 -07:00
AurelienUoU c2c4e78639 Add pip_add benchmark 2018-12-11 15:29:48 -07:00
AurelienUoU f5ea3ff233 Add an autochecked configuration free testbench 2018-12-11 14:44:13 -07:00
tangxifan 72fbd8d6a8 update blif reader to identify clock signals 2018-12-10 13:28:44 -07:00
AurelienUoU a69c2e1882 Add security in checking to avoid simulation glitch error 2018-12-10 09:46:16 -07:00
AurelienUoU 7020d9b4b6 Edit waveform generator + fix clock mapping in autochecked testbench 2018-12-09 15:48:59 -07:00
AurelienUoU 5e94b7093d Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench) 2018-12-08 22:57:54 -07:00
Aur??Lien ALACCHI 10866d1852 Correct verilog syntax error in autocheck testbench 2018-12-08 17:40:23 -07:00