9d9840d9b7
[Arch] Add architecture using multi-mode DFFs
2021-04-21 19:49:48 -06:00
e3dafe99da
[Arch] Revert to old version arch due to editing by mistake
2021-04-16 20:58:32 -06:00
16e02ef485
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
2021-04-16 20:47:39 -06:00
4239bb4e68
[Arch] Patch architecture files using multi-mode DFFs
2021-04-16 19:59:55 -06:00
f2f7f010ea
[Arch] Add new architectures using DFF with reset in VPR
2021-04-16 19:26:18 -06:00
64294ae4eb
[Doc] Update README for architecture files due to new architecture features
2021-04-16 19:25:54 -06:00
44d97ead86
Merge branch 'master' into hetergeneous_arch
2021-03-23 17:05:03 -06:00
fdec72b5bc
[Arch] Add an example architecture with 8-bit single-mode multiplier
2021-03-23 15:35:06 -06:00
911979a731
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
2021-03-20 18:04:59 -06:00
910f8471dd
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
2021-03-17 15:10:05 -06:00
ad25944e59
[Arch] Patched superLUT architecture example when trying adder8 synthesis script
2021-02-23 19:00:27 -07:00
ca135f3325
[Arch] Add flagship architecture with 8-clock
2021-02-22 15:01:18 -07:00
1c09c55e9f
[Arch] Add hetergenenous 8-clock FPGA architecture
2021-02-22 13:38:50 -07:00
0ac75723af
[Arch] Add new architecture with 8 clocks
2021-02-22 11:00:45 -07:00
b9c2564a7e
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
2021-02-22 10:49:21 -07:00
7dcc14d73f
[Arch] Bug fix in the example arch with super LUT
2021-02-09 15:52:22 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
...
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
dc09c47411
[Arch] Remove packable from architecture files and replace with disable_packing
2021-02-04 18:03:56 -07:00
66bc370c4d
[Arch] Use disable_packing in architecture library
2021-02-04 16:29:03 -07:00
a4c266d59a
[Arch] Add pack patterns for soft adders; Still fail in packing
2021-02-03 19:11:15 -07:00
cac1160bf7
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
2021-02-03 11:20:56 -07:00
021520783b
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
2021-02-02 15:49:43 -07:00
10302752a7
[Arch] Bug fix in architecture. Now soft adder modes are accepted
2021-02-01 13:43:39 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
9bbf214456
[Arch] Update the caravel architecture
2021-01-29 17:00:17 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
16b4e89326
[Doc] Update documentation for VPR architectures
2021-01-12 17:57:40 -07:00
7ccdff4543
[Arch] Add an architecture using 4 clocks
2021-01-12 17:55:57 -07:00
aaf582acc5
[Arch] Bug fix
2021-01-10 11:05:57 -07:00
f21d22f691
[Doc] Update README for new architectures
2021-01-10 10:54:59 -07:00
853e7b1a40
[Arch] Add vpr architecture where I/O can be either combinational or registered
2021-01-10 10:54:09 -07:00
891e2f8aa3
Adding arch xml from SOFA repo. Also updating the script with its file location
2020-12-16 04:14:18 -08:00
6001da3a40
[Arch] Bug fix in tileable I/O arch example
2020-12-04 17:56:54 -07:00
1d0bdcfeca
[Arch] Simplify the grid layout modeling
2020-12-04 17:38:44 -07:00
1c3f625e41
[Arch] Force empty tiles at corners for tileable I/O arch example
2020-12-04 17:11:06 -07:00
186eb0f0a4
[Arch] Add tileable I/O architecture example
2020-12-04 15:59:39 -07:00
7a0a3398d4
[Arch] Add new architecture to test global reset ports defined thru tile ports
2020-11-30 17:43:41 -07:00
a60bd4d14a
[Arch] Bug fix in nature fracturable architecture
2020-11-25 22:48:26 -07:00
eda671592e
[Doc] Update README about new keyword about fracturable LUT
2020-11-25 22:12:56 -07:00
0f841aa6d1
[Arch] Add an example architecture using native fracturable LUT
2020-11-25 22:11:14 -07:00
a6531d9e8d
[Arch] Add k4 arch using global clock from tile port (with zero fc)
2020-11-10 19:17:34 -07:00
bce8233019
[Arch] Bug fix in caravel arch
2020-11-04 20:58:58 -07:00
aebf7453d0
[Arch] Add architecture files with compatible I/O capacity with caravel SoC
2020-11-04 16:57:00 -07:00
cf455df555
[Arch] Add architecture for bottom-right and top-left tile organization
2020-11-04 16:24:36 -07:00
46ca406f10
[Arch] Add a new vpr architecture with new tile organization
2020-11-04 16:20:01 -07:00
049ca14461
[Doc] Add new naming rules for vpr architecture files
2020-11-04 16:17:56 -07:00
3b49e6d090
[Arch] Patch embedded IO architecture by forcing only 1 pad per block
2020-11-02 15:39:31 -07:00
a7e7fa2005
[Arch] Update arch with true embedded I/O definition
2020-11-02 13:29:40 -07:00
8c8190047f
[Arch] Rename architecture files for embedded I/Os
2020-11-02 13:15:19 -07:00
795b30f76b
[Arch] Add VPR architecture with partial pin equivalence
2020-11-02 11:54:25 -07:00
951a47b19c
[Architecture] Add k4 series architecture using pattern-based local routing
2020-09-23 16:05:39 -06:00
70b8b02f74
[Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier
2020-09-22 15:32:11 -06:00
8a3934b749
[Architecture Add vpr architecture for k4n4 using multiple wire segments
2020-09-22 12:35:39 -06:00
daf776b7b1
[Architecture] Add k4n4 architecture with bram block for basic tests
2020-09-22 12:22:32 -06:00
7a6f5a06f7
[Architecture] Add a k4n4 architecture with carry chain to quick test
2020-09-22 11:33:56 -06:00
aa5f5fc7e0
[Architecture] Bring back pin equivalence for no local routing architecture
2020-09-21 22:22:39 -06:00
a8a269aa82
[Architecture] Temporary patch for the no local routing architecture
2020-09-21 19:51:23 -06:00
7a57cc9cf4
[Architecture] A new device layout to k4n4 to test untileable architecture
2020-09-21 18:36:50 -06:00
2bbfcb5753
[Architecture] Add a new device layout to k4n4 for testing tileable routing
2020-09-21 18:34:31 -06:00
e1c5947143
[Architecture] Add auto layout and fixed layout to architectures
2020-09-21 18:01:51 -06:00
d7f8b3abad
[Architecture] Add k4 N4 untilable architecture
2020-09-21 17:44:37 -06:00
e9c0e90544
[Architecture] Add a VPR architectue using fracturable LUT4
2020-09-21 17:37:26 -06:00
ca1bafc688
[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture
2020-09-16 19:26:12 -06:00
c22d8e2421
[Architecture] Bug fix in no local routing architecture
2020-09-16 18:07:52 -06:00
f5b7ac6269
[OpenFPGA Architecture] Add a new architecture with no local routing
2020-09-16 18:04:55 -06:00
030d7f02f8
[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
2020-09-16 17:30:08 -06:00
3c0faf0021
[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
2020-09-16 17:27:24 -06:00
6c925dcded
[regression test] Add more tests for thru channels and deploy to CI
2020-08-19 20:11:37 -06:00
881672d46a
update thru channel arch for avoid buggy pin locations
2020-08-19 19:52:35 -06:00
3273f441fe
bug fix in the flagship vpr arch
2020-08-19 15:23:20 -06:00
d7efdf35b6
add custom pin location to the flagship vpr arch with frac mem and dsp
2020-08-19 11:15:25 -06:00
3ee4e10aa8
bug fix in the frac mem & DSP vpr arch
2020-08-18 17:25:45 -06:00
f833e0ec66
add a flagship architecture using fracturable memory and dsp
2020-08-17 17:49:51 -06:00
1ca2829868
update readme for vpr architecture naming
2020-08-17 13:54:26 -06:00
534c609e17
add fixed layouts to a flagship architecture to test bitstream generation runtime
2020-07-28 11:51:50 -06:00
f754c8af06
use k6_n10 architecture to reduce CI runtime
2020-07-22 13:45:55 -06:00
1e6955aaa4
rename arch directory to be clear for its usage
2020-07-04 19:13:28 -06:00
tangxifan
AurelienAlacchi
Lalit Sharma