a4d5172b7c
[Test] Fixed bugs that causes VPR failed
2022-02-18 12:31:29 -08:00
7176037bc4
[Test] Added a new test about bus group
2022-02-18 12:26:00 -08:00
f002c79a61
[Test] Adapt pin constraints due to changes in pin names
2022-02-15 16:06:46 -08:00
b533fd17d5
[Test] Rework pin constraints that cause problems
2022-02-15 15:41:16 -08:00
9ef7ad64d8
[Test] Simplify paths
2022-02-15 15:35:21 -08:00
f8ef3df560
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
2022-01-26 11:41:48 -08:00
3b7588cd48
[Test] Rename test case to be consistent with the name of options
2022-01-26 11:25:54 -08:00
6b26ed0819
[Test] Add test cases on writing gsb files
2022-01-26 11:22:39 -08:00
23795d6474
[Test] Update golden netlists
2022-01-25 20:37:08 -08:00
a9e6b7c12e
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
2022-01-25 20:33:49 -08:00
fedb1bd2e3
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
2022-01-25 16:41:36 -08:00
6e778a74ee
[Test] Add golden reference for files outputted without time stamp
2022-01-25 16:24:25 -08:00
2bee59c6ca
[Test] Add the testcase to validate ``--no_time_stamp``
2022-01-25 16:21:15 -08:00
758453f725
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
397f2e71f1
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
2022-01-19 20:43:26 +05:00
588ee14920
Merge branch 'master' into issue-483
2022-01-18 13:38:12 +05:00
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
598c5e6b75
Test case for yosys-only flow added
2022-01-14 15:37:47 +05:00
1ea56b2d18
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-11-18 00:00:55 +05:00
b332a5a1b4
Added 'basic_tests/verific_test' test-case.
2021-11-01 18:20:57 +05:00
b2c4e3314e
[Test] Bug fix in test cases
2021-10-11 10:28:09 -07:00
8566e2a0cd
[Test] Renaming test case to follow naming convention as other fabric key test cases
2021-10-11 09:56:23 -07:00
b8b02d37d5
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
2021-10-11 09:53:23 -07:00
6122863548
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
2021-10-09 20:44:28 -07:00
a1eaacf5a8
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
2021-10-06 12:12:15 -07:00
b98a8ec718
[Test] Added the dedicated test case for fixed shift register clock frequency
2021-10-06 12:09:26 -07:00
b21f212031
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
2021-10-05 11:39:53 -07:00
52569f808e
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
2021-10-05 10:57:33 -07:00
fa1908511d
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
2021-10-04 16:36:20 -07:00
dda147e234
[Flow] Add an example simulation setting file for defining programming shift register clocks
2021-10-01 11:04:23 -07:00
89a97d83bd
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
2021-09-29 16:28:06 -07:00
4400dae108
[Test] Bug fix in the wrong arch name
2021-09-28 11:40:25 -07:00
dae3554fd4
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
2021-09-28 11:27:49 -07:00
655b195d8b
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
2021-09-22 15:56:44 -07:00
b0aaab9c03
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
2021-09-22 11:32:13 -07:00
abfa380333
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
2021-09-22 11:27:09 -07:00
51fc222d61
[Test] Added a new test case for multi-region QL memory bank
2021-09-22 10:01:33 -07:00
1412121541
[Test] Added a new test to validate the fabric key parser for QL memory bank
2021-09-21 16:20:24 -07:00
dc2d1d1c3c
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
2021-09-21 15:42:20 -07:00
60fc3ab36c
[Test] Added a new test case for the WLR memory bank
2021-09-20 11:20:36 -07:00
b82cfdf555
[Test] Add the QL memory bank test to regression test cases
2021-09-09 09:29:21 -07:00
64dcdaec61
[Test] Update all the tasks that use counter benchmark
2021-07-02 17:29:13 -06:00
3cbe266c44
[Test] Bug fix on the test case for multi-mode FF and pin constraints
2021-07-02 15:27:27 -06:00
3aacce2a96
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
2021-07-02 14:04:42 -06:00
edd5be2cae
[CI] Added testcase for benchmark variable
2021-07-02 12:51:34 -06:00
5286f9ba25
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
2021-07-02 11:39:00 -06:00
9eeec05a1f
[Test] Bug fix
2021-06-29 19:55:07 -06:00
f32ffb6d61
[Test] Bug fix
2021-06-29 18:51:28 -06:00
c6089385b0
[Misc] Bug fix
2021-06-29 18:34:41 -06:00
5f5a03f17f
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
2021-06-29 18:28:38 -06:00
2c1692e6dc
[Test] Bug fix
2021-06-29 17:54:25 -06:00
30c2f597f2
[Test] Added two cases to validate testbench generation without self checking
2021-06-29 16:06:15 -06:00
c62666e7c3
[Test] Use proper template for some failing tests
2021-06-09 14:24:34 -06:00
462326aaa5
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
2021-06-07 21:50:00 -06:00
5ecd975ec7
[Test] Bug fix
2021-06-07 19:20:10 -06:00
9556f994b4
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
2021-06-07 17:49:40 -06:00
a67196178e
[Test] Now use 'write_full_testbench' in configuration frame test cases
2021-06-07 13:58:15 -06:00
27fa15603a
[Tool] Patch test case due to changes in the template script
2021-06-04 18:17:47 -06:00
5f96d440ec
[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
2021-06-04 11:48:05 -06:00
ec203d3a5c
[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
2021-06-04 11:35:23 -06:00
2068291de0
[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
2021-06-04 11:32:49 -06:00
aa4e1f5f9a
[Test] Update test case which uses write_full_testbench openfpga shell script
2021-06-04 11:29:43 -06:00
ebe30fc070
[Test] Deploy write full testbench to multi-head configuration chain test case
2021-06-03 17:08:33 -06:00
1e9f6eb439
[Test] update configuration chain test to use new testbench
2021-06-03 15:53:27 -06:00
f1658cb735
[Test] Deploy blinking to test cases
2021-05-06 15:17:45 -06:00
8046b16c15
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
2021-04-21 14:04:34 -06:00
da95da933b
[Test] Add pin constraint file to map reset to correct FPGA pins
2021-04-17 15:04:26 -06:00
7172fc9ea1
[Test] Patch test for architecture using asynchronous DFFs
2021-04-16 20:48:37 -06:00
93be81abe1
[Test] Add test case for architecture using DFF with reset
2021-04-16 20:00:48 -06:00
a4893e27cf
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
2021-04-11 17:26:27 -06:00
d12a8a03fd
[Test] Update test case using yosys bram parameters
2021-03-16 19:52:17 -06:00
73b06256d0
[Test] Deploy the new yosys script supporting BRAM to regression tests
2021-03-16 16:52:59 -06:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
af0646260c
[Test] Bug fix in pin constraints
2021-01-19 17:44:05 -07:00
186f2f1968
[Test] Use pin constraint in multi-clock test case
2021-01-19 17:42:40 -07:00
e17a5cbbf2
[Test] Rename to pin constraint to comply with libpcf requirement
2021-01-19 15:52:51 -07:00
ab25e1af5f
[Test] Add example XML for net mapping between benchmark to FPGA
2021-01-19 09:29:21 -07:00
ea9d6bfe91
[Flow] Update the design constraint file to follow bug fix in parser
2021-01-17 10:41:01 -07:00
dd74f05a31
[Test] Add repack constraints to tests
2021-01-17 10:35:36 -07:00
d0e05b3575
[Lib] Now use pb_type in design constraints instead of physical tiles
2021-01-16 21:35:43 -07:00
8578c1ecac
[Flow] Rename the design contraint file syntax
2021-01-16 15:35:13 -07:00
9154cfdeec
[Flow] Add comments for the design constraint file
2021-01-16 15:34:01 -07:00
6ab0f71896
[Test] Add an example of repack pin constraints file
2021-01-16 14:38:39 -07:00
3b5394b45f
[Test] Now use dedicated simulation settings for the 4-clock architecture
2021-01-14 15:40:16 -07:00
314e458632
[Test] Update task configuration to use post-yosys .v file in verification
2021-01-13 15:42:45 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
250adb01cf
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
2021-01-13 13:18:31 -07:00
99e2a068fb
[Test] Add a test case for multi-clock
2021-01-12 18:06:25 -07:00
43418cd76b
[Test] Deploy pipeplined and2 to test cases
2021-01-10 10:28:22 -07:00
06af30ef10
[Test] Add test case for the SCFF usage in configuration chain
2021-01-04 17:30:19 -07:00
6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
...
Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
0cb8457e21
[Test] Add test case for tileable I/O
2020-12-04 16:02:47 -07:00
179b0ce304
[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
2020-11-30 18:11:47 -07:00
27a480b5f8
[Test] arch name fix in the test case
2020-11-30 17:45:54 -07:00
a1d3b439d3
[Test] Add a new test case to define a global reset port from a global tile port
2020-11-30 17:19:12 -07:00
7db030018c
[Bug] Fixed variable file location
2020-11-25 22:44:40 -07:00
fefba0db59
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
2020-11-25 17:29:53 -07:00
1d993296d8
[Flow] Example of using test variable in task conf
2020-11-25 17:25:12 -07:00
655da9f3d0
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
2020-11-22 16:37:19 -07:00
845436fa71
[Test] Add sequential benchmark for global tile clock test case
2020-11-17 14:34:54 -07:00
tangxifan
Aram Kostanyan
Awais Abbas
nadeemyaseen-rs
Ganesh Gore
AurelienAlacchi