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OpenFPGA
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5,044 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

316 Commits

Author SHA1 Message Date
tangxifan e60d7d12b7 [Lib] Fixed a bug in writer 2022-02-17 17:12:07 -08:00
tangxifan 4b3f906f11 [Lib] Fixed all the syntax errors 2022-02-17 17:09:03 -08:00
tangxifan 27627bf5b4 [Lib] Add an example XML for bus group unit tests 2022-02-17 16:22:01 -08:00
tangxifan 0d7e949166 [Lib] Add unit test for bus group 2022-02-17 16:21:12 -08:00
tangxifan 76cf4e1662 [Lib] Add reader and writer for bus group 2022-02-17 16:17:37 -08:00
tangxifan 1edaa04715 [Lib] Adding XML parser for the bus group 2022-02-17 15:50:44 -08:00
tangxifan b44701bc2c [Lib] Adding the 1st version of bus group data structure 2022-02-17 15:02:37 -08:00
tangxifan a9e6b7c12e [FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled 2022-01-25 20:33:49 -08:00
tangxifan 25143d07f1 [FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files 2022-01-25 13:37:54 -08:00
tangxifan 4e2df9d69c [Lib] Bug fix in unintialized memory in fabric key 2021-10-10 17:59:11 -07:00
tangxifan 92eebd9abb [Lib] Upgrade fabric key writer to support the BL/WL shift register banks 2021-10-07 17:05:35 -07:00
tangxifan eddafb42c8 [Lib] Upgrade parser for fabric key to support shift register banks 2021-10-07 15:38:42 -07:00
tangxifan a15798a4e1 [Lib] Upgrade fabric key data structure to support shift register bank definitions 2021-10-07 14:42:21 -07:00
tangxifan 9693a269ee [FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank 2021-10-07 11:31:16 -07:00
tangxifan bf473f50f8 [FPGA-Verilog] Correct bugs in logging clock frequencies 2021-10-06 11:55:57 -07:00
tangxifan fcb5470baa [Lib] Add validator to check if a clock is constrained in simulation settings 2021-10-06 11:48:23 -07:00
tangxifan 3d062872de [Lib] Upgrade openfpga arch parser to error out for unsupported configuration protocol settings 2021-10-05 14:08:01 -07:00
tangxifan 977d81679d [Engine] Upgrade check codes for WL CCFF 2021-10-01 17:23:10 -07:00
tangxifan 7b010ba0f4 [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
tangxifan 4926c323e7 [Engine] Bug fix due to the optional syntax ``num_bank`` were required in XML 2021-09-29 16:32:29 -07:00
tangxifan 834bdd2b07 [Engine] Updating fabric generator to support BL/WL shift registers. Still WIP 2021-09-28 17:29:03 -07:00
tangxifan afd03d7eb7 [Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers 2021-09-28 15:56:07 -07:00
tangxifan 0a2979d616 [Engine] Update readarchopenfpga library by adding new syntax ``num_banks`` as well as update arch writer for BL/WL protocols 2021-09-28 14:20:35 -07:00
tangxifan 8b72447dad [FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs 2021-09-24 18:07:07 -07:00
tangxifan a49e3fe57a [FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank 2021-09-24 16:30:18 -07:00
tangxifan 5f7617b682 [Engine] Clear up compiler warnings in circuit library 2021-09-24 15:18:50 -07:00
tangxifan f735c10b84 [Engine] Clear up compiler warnings 2021-09-24 15:18:31 -07:00
tangxifan be4c850d2d [Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs 2021-09-24 12:03:35 -07:00
tangxifan 6645b70ae3 [Engine] Upgrade parser to support BL/WL protocols 2021-09-23 14:25:25 -07:00
tangxifan d4e3445153 [Engine] update internal data structure for new syntax in configuration protocol 2021-09-22 17:32:45 -07:00
tangxifan e09ab2298e [Engine] Bug fix in fabric key parser on identifying invalid coordinate 2021-09-21 16:45:14 -07:00
tangxifan 7688c0570f [Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key 2021-09-21 15:08:08 -07:00
tangxifan 36a4da863c [Engine] Support WLR port in OpenFPGA architecture file and fabric generator 2021-09-20 16:05:36 -07:00
tangxifan 5759f5f35b [Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder 2021-09-03 17:55:23 -07:00
tangxifan 9074bffa68 [Tool] Support customized default value in pin constraint file 2021-07-01 23:43:19 -06:00
tangxifan fed975c52a [Tool] Add postfix removal support in write_io_mapping command 2021-06-18 16:13:50 -06:00
tangxifan db9bb9124e [Tool] Add report bitstream distribution command to openfpga shell 2021-05-07 11:41:25 -06:00
tangxifan 01b3a96e4b [Tool] Add report bitstream distribution functionality to architecture bitstream library 2021-05-07 11:22:01 -06:00
tangxifan 148da80869 [Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes 2021-04-24 14:53:29 -06:00
tangxifan 96ce6b545f [Tool] Patch repack to consider design constraints for pins that are not equivalent 2021-04-21 13:53:08 -06:00
tangxifan 5364b94cf8 [Tool] Update bitstream setting parser/writer to support interconnect-related syntax 2021-04-19 13:42:12 -06:00
tangxifan 0b49c22682 [Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks 2021-04-18 16:11:11 -06:00
tangxifan 6550ea3dfa [Tool] Rework pin constarint API to avoid expose raw data to judge for developers 2021-04-18 12:02:49 -06:00
tangxifan 6e9b24f9bf [Tool] Patch the invalid pin constraint net name 2021-04-17 19:56:30 -06:00
tangxifan d95a1e2776 [Tool] Encapulate search function in PinConstraint data structure 2021-04-17 17:31:55 -06:00
tangxifan d877a02534 [Tool] Patch the extended bitstream setting support on mode-select bits 2021-03-10 21:28:09 -07:00
tangxifan 85640a7403 [Tool] Extend bitstream setting to support mode bits overload from eblif file 2021-03-10 20:45:48 -07:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
tangxifan 73461971d2 [Tool] Bug fix for printing single-bit ports in Verilog netlists 2021-02-28 16:12:57 -07:00
tangxifan 7a5dd1bc02 [Tools] Patch circuit library for dummy circuit models without any ports 2021-02-24 10:36:48 -07:00
tangxifan b2984b46ee [Tool] Upgrade libopenfpga to support superLUT-related XML syntax 2021-02-09 21:15:57 -07:00
tangxifan faabdab815 [Tool] Remove redundant tab in bitstream setting writer 2021-02-01 18:04:21 -07:00
tangxifan d5b1cc5ec7 [Tool] Bug fix in parser for bitstream settings 2021-02-01 18:01:42 -07:00
tangxifan f102e84497 [Tool] Add bitstream setting file to openfpga library 2021-02-01 17:43:46 -07:00
tangxifan 3b7762ef85 [Lib] Now try to call undefined command will cause a error code to return 2021-01-24 17:44:51 -07:00
tangxifan a8158322ef [Tool] Bug fix in setting command execution status in OpenFPGA shell 2021-01-24 17:25:03 -07:00
tangxifan fd0e73a9bb [Tool] Enhance return code for openfpga shell 2021-01-24 14:48:27 -07:00
tangxifan 8cac3291cb [Tool] Add batch mode to openfpga shell execution 2021-01-24 14:33:58 -07:00
tangxifan 4cc8b08a6c [Tool] Add openfpga version display 2021-01-23 16:38:00 -07:00
tangxifan 0670c2de59 [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00
tangxifan ecd955124b [Lib] Add libpcf to CMakelist and bug fix 2021-01-19 15:51:14 -07:00
tangxifan 52ac7826eb [Lib] Add a library of parser/writer for pin constraint file (PCF) 2021-01-19 15:45:45 -07:00
tangxifan ea9d6bfe91 [Flow] Update the design constraint file to follow bug fix in parser 2021-01-17 10:41:01 -07:00
tangxifan 113119bd8e [Lib] Fix the bug in repack design constraint parser 2021-01-17 10:39:55 -07:00
tangxifan 2efe513122 [Tool] Now repack consider design constraints; test pending 2021-01-16 21:57:17 -07:00
tangxifan d0e05b3575 [Lib] Now use pb_type in design constraints instead of physical tiles 2021-01-16 21:35:43 -07:00
tangxifan b86adabe69 [Lib] Remove unused data storage from repack design constraints 2021-01-16 21:14:52 -07:00
tangxifan 706e84bb62 [Lib] Bug fix in testing program 2021-01-16 18:15:56 -07:00
tangxifan 67c54c4d3b [Lib] Bug fix in the repack design constraint lib 2021-01-16 17:34:22 -07:00
tangxifan ad7a54db1b [Tool] Add repack dc library to compilation 2021-01-16 17:20:59 -07:00
tangxifan 9d80f1ab39 [Lib] Add test program to the library of repack design constraints 2021-01-16 17:18:42 -07:00
tangxifan 03b5bcc244 [Lib] Add XML writer for repack design constraints 2021-01-16 17:15:31 -07:00
tangxifan 2a7601fb7e [Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints 2021-01-16 17:14:51 -07:00
tangxifan f1bfa2ef8c [Lib] Add XML parser for repack design constraints 2021-01-16 17:03:01 -07:00
tangxifan 8be12b6e82 [Lib] Add example design constraint file 2021-01-16 16:36:10 -07:00
tangxifan a926c74ae5 [Lib] Add CMake script to compile the repack design constraint library 2021-01-16 16:35:46 -07:00
tangxifan b57dc7b898 [Lib] Add repack design constraint library 2021-01-16 16:35:13 -07:00
tangxifan b8e4675a3a [Tool] Add missing file 2021-01-15 14:48:19 -07:00
tangxifan 87b2c1f3b8 [Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation 2021-01-15 12:01:53 -07:00
tangxifan 852f5bb72e [Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers 2021-01-14 15:38:24 -07:00
tangxifan 4124777948 [Tool] Set (x,y) to be optional XML syntax in tile annotation 2021-01-09 18:56:41 -07:00
tangxifan 9a441fa5cc [Tool] Upgrade openfpga to support extended global tile port definition 2021-01-09 18:47:12 -07:00
tangxifan cc91a0aebd [Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder 2021-01-04 17:14:26 -07:00
tangxifan cb34be0dc0 [Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements 2021-01-04 15:13:54 -07:00
tangxifan d195b9e32c [Tool] Bug fix in XML syntax to define default values for a global tile port 2020-12-02 17:03:48 -07:00
tangxifan e959821813 [Tool] Enhance internal check functions for tile annotation 2020-11-11 13:59:24 -07:00
tangxifan 4dc0fb81c5 [Tool] Bug fix for clang compilation error 2020-11-10 20:32:58 -07:00
tangxifan c61ec5a8b8 [Tool] Bug fix for defining global ports from tiles 2020-11-10 20:31:14 -07:00
tangxifan 67af145455 [Tool] Add XML writer for tile annotation 2020-11-10 14:51:46 -07:00
tangxifan 6fbdbe68ae [Tool] Add tile annotation parser 2020-11-10 14:32:24 -07:00
tangxifan 0a273ffab6 [Tool] Bug fix in the tight requirements on CCFF circuit model 2020-11-06 11:16:46 -07:00
tangxifan ba0120bd76 [Tool] Remove the limitation on requiring Qb ports for CCFF 2020-11-06 11:10:04 -07:00
tangxifan 37c10f0cb5 [Tool] Add mappable I/O support and enhance I/O support 2020-11-04 20:21:49 -07:00
tangxifan f1ce816d6c [Tool] Force inout port to be mandatory for I/O cells 2020-11-02 15:14:02 -07:00
tangxifan e850dd5314 [Tool] Relax checking codes for embedded I/O circuit models 2020-11-02 13:54:31 -07:00
tangxifan b78f8bec16 [Tool] Bug fixed for multi-region configuration frame 2020-10-30 21:19:20 -06:00
tangxifan 1e70825383 [OpenFPGA Tool] Add XML syntax for configurable regions 2020-09-28 13:51:43 -06:00
tangxifan 052b8b71c7 [OpenFPGA Tool] Bug fix in the XML parser for fabric regions 2020-09-27 20:54:58 -06:00
tangxifan 491433fae2 [OpenFPGA Tool] Update XML parser for fabric regions 2020-09-27 20:41:01 -06:00
tangxifan 48b2bff0d9 [OpenFPGA Tool] Update fabric key data structure to support regions 2020-09-27 20:08:11 -06:00