[Lib] Adding the 1st version of bus group data structure

libopenfpga/CMakeLists.txt

@@ -7,3 +7,4 @@ add_subdirectory(libfabrickey)
 add_subdirectory(librepackdc)
 add_subdirectory(libfpgabitstream)
 add_subdirectory(libpcf)
+add_subdirectory(libbusgroup)

libopenfpga/libbusgroup/CMakeLists.txt

@@ -0,0 +1,35 @@
+cmake_minimum_required(VERSION 3.9)
+
+project("libbusgroup")
+
+file(GLOB_RECURSE EXEC_SOURCES test/*.cpp)
+file(GLOB_RECURSE LIB_SOURCES src/*.cpp)
+file(GLOB_RECURSE LIB_HEADERS src/*.h)
+files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
+
+#Remove test executable from library
+list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCES})
+
+#Create the library
+add_library(libbusgroup STATIC
+            ${LIB_HEADERS}
+            ${LIB_SOURCES})
+target_include_directories(libbusgroup PUBLIC ${LIB_INCLUDE_DIRS})
+set_target_properties(libbusgroup PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
+
+#Specify link-time dependancies
+target_link_libraries(libbusgroup
+                      libopenfpgautil
+                      libarchopenfpga
+                      libvtrutil
+                      libpugixml
+                      libpugiutil)
+
+#Create the test executable
+foreach(testsourcefile ${EXEC_SOURCES})
+    # Use a simple string replace, to cut off .cpp.
+    get_filename_component(testname ${testsourcefile} NAME_WE)
+    add_executable(${testname} ${testsourcefile})
+    # Make sure the library is linked to each test executable
+    target_link_libraries(${testname} libbusgroup)
+endforeach(testsourcefile ${EXEC_SOURCES})

libopenfpga/libbusgroup/src/bus_group.cpp

@@ -0,0 +1,68 @@
+#include <algorithm>
+
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "bus_group.h"
+
+/************************************************************************
+ * Member functions for class BusGroup
+ ***********************************************************************/
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+BusGroup::BusGroup() {
+  return;
+}
+
+/************************************************************************
+ * Public Accessors : aggregates
+ ***********************************************************************/
+BusGroup::bus_group_range BusGroup::buses() const {
+  return vtr::make_range(bus_ids_.begin(), bus_ids_.end());
+}
+
+/************************************************************************
+ * Public Accessors : Basic data query 
+ ***********************************************************************/
+openfpga::BasicPort BusGroup::bus_port(const BusGroupId& bus_id) const {
+  /* validate the bus_id */
+  VTR_ASSERT(valid_bus_id(bus_id));
+  return bus_ports_[bus_id]; 
+}
+
+bool BusGroup::empty() const {
+  return 0 == bus_ids_.size();
+}
+
+/************************************************************************
+ * Public Mutators
+ ***********************************************************************/
+void BusGroup::reserve_buses(const size_t& num_buses) {
+  bus_ids_.reserve(num_buses);
+  bus_ports_.reserve(num_buses);
+  bus_pin_indices_.reserve(num_buses);
+  bus_pin_names_.reserve(num_buses);
+}
+
+BusGroupId BusGroup::create_bus(const openfpga::BasicPort& bus_port) {
+  /* Create a new id */
+  BusGroupId bus_id = BusGroupId(bus_ids_.size());
+  
+  bus_ids_.push_back(bus_id);
+  bus_ports.push_back(bus_port);
+  bus_pin_indices_.emplace_back();
+  bus_pin_names_.emplace_back();
+  
+  return bus_id;
+}
+
+/************************************************************************
+ * Internal invalidators/validators 
+ ***********************************************************************/
+/* Validators */
+bool BusGroup::valid_bus_id(const BusGroupId& bus_id) const {
+  return ( size_t(bus_id) < bus_ids_.size() ) && ( bus_id == bus_ids_[bus_id] ); 
+}
+

libopenfpga/libbusgroup/src/bus_group.h

@@ -0,0 +1,77 @@
+#ifndef BUS_GROUP_H
+#define BUS_GROUP_H
+
+/********************************************************************
+ * This file include the declaration of pin constraints
+ *******************************************************************/
+#include <string>
+#include <map>
+#include <array>
+
+/* Headers from vtrutil library */
+#include "vtr_vector.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+
+#include "bus_group_fwd.h"
+
+/********************************************************************
+ * A data structure to describe the bus-to-pin mapping
+ * This data structure may include a number of buses
+ * each of which has:
+ * - a unique id and name
+ * - a number of pins with names and index which are flatten from the bus
+ *
+ * Typical usage:
+ * --------------
+ *   // Create an object of bus group
+ *   BusGroup bus_group;
+ *   // Create a new port
+ *   BasicPort bus_a("BusA", 0, 3)
+ *   // Add a bus
+ *   BusGroupId bus_group_id = bus_group.create_bus(bus_a);
+ *
+ *******************************************************************/
+class BusGroup {
+  public: /* Types */
+    typedef vtr::vector<BusGroupId, BusGroupId>::const_iterator bus_group_iterator;
+    /* Create range */
+    typedef vtr::Range<bus_group_iterator> bus_group_range;
+  public:  /* Constructors */
+    BusGroup();
+  public: /* Accessors: aggregates */
+    bus_group_range buses() const;
+  public: /* Public Accessors: Basic data query */
+    /** Get port information of a bus with a given id */
+    openfpga::BasicPort BusGroup::bus_port(const BusGroupId& bus_id) const;
+
+    /* Check if there are any buses */
+    bool empty() const;
+
+  public: /* Public Mutators */
+    /* Reserve a number of buses to be memory efficent */
+    void reserve_buses(const size_t& num_buses);
+
+    /* Add a bus to storage */
+    BusGroupId create_bus(const openfpga::BasicPort& bus_port);
+
+  public: /* Public invalidators/validators */
+    /* Show if the pin constraint id is a valid for data queries */
+    bool valid_bus_id(const BusGroupId& bus_id) const;
+
+  private: /* Internal data */
+    /* Unique ids for each bus */
+    vtr::vector<BusGroupId, BusGroupId> bus_ids_;
+
+    /* Port information of each bus */
+    vtr::vector<BusGroupId, openfpga::BasicPort> bus_ports_;
+
+    /* Indices of each pin under each bus */
+    vtr::vector<BusGroupId, std::vector<int>> bus_pin_indices_;
+
+    /* Name of each pin under each bus */
+    vtr::vector<BusGroupId, std::vector<std::string>> bus_pin_names_;
+};
+
+#endif

libopenfpga/libbusgroup/src/bus_group_fwd.h

@@ -0,0 +1,24 @@
+/************************************************************************
+ * A header file for BusGroup class, including critical data declaration
+ * Please include this file only for using any PinConstraints data structure
+ * Refer to bus_group.h for more details 
+ ***********************************************************************/
+
+/************************************************************************
+ * Create strong id for BusGroup to avoid illegal type casting 
+ ***********************************************************************/
+#ifndef BUS_GROUP_FWD_H
+#define BUS_GROUP_FWD_H
+
+#include "vtr_strong_id.h"
+
+struct bus_group_id_tag;
+struct bus_pin_id_tag;
+
+typedef vtr::StrongId<bus_group_id_tag> BusGroupId;
+typedef vtr::StrongId<bus_pin_id_tag> BusPinId;
+
+/* Short declaration of class */
+class BusGroup;
+
+#endif