riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Lib] Add an example XML for bus group unit tests

This commit is contained in:
tangxifan 2022-02-17 16:22:01 -08:00
parent 0d7e949166
commit 27627bf5b4
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
libopenfpga/libbusgroup/example/bus_group_example.xml Normal file
View File

@ -0,0 +1,8 @@
<bus_group>
<bus name="i_addr[0:3]">
<pin id="0" name="i_addr_0_"/>
<pin id="1" name="i_addr_1_"/>
<pin id="2" name="i_addr_2_"/>
<pin id="3" name="i_addr_3_"/>
</bus>
</bus_group>