tangxifan
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1b91c32121
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-21 17:59:55 -06:00 |
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tangxifan
|
41954056ce
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many bug fixing for tileable rr_graph generator. Still debugging
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2019-06-21 17:58:46 -06:00 |
AurelienUoU
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0a42f6a796
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-21 15:47:14 -06:00 |
|
AurelienUoU
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c0d7099cd6
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Allow CB on top of blocks with height > 1
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2019-06-21 15:46:05 -06:00 |
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tangxifan
|
d48fd959a9
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keep bug fixing for tileable rr_graph generator
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2019-06-20 22:30:26 -06:00 |
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tangxifan
|
548242b368
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plug-in tileable rr generator which can be enable by a XML property
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2019-06-20 21:06:26 -06:00 |
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tangxifan
|
cf82d87e11
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-20 18:18:20 -06:00 |
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tangxifan
|
baab9c4a21
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basically finished the coding of tileable rr_graph generator. testing to go
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2019-06-20 18:17:07 -06:00 |
Baudouin Chauviere
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be25b6dd66
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-20 14:11:03 -06:00 |
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Baudouin Chauviere
|
3bd6c40a10
|
Report timing modified to have only one liners
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2019-06-20 14:10:39 -06:00 |
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AurelienUoU
|
a7502bb43b
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Avoid configuration bits for module wihch don't require them
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2019-06-20 09:40:41 -06:00 |
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tangxifan
|
e7f2bd3b7c
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-19 21:31:54 -06:00 |
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tangxifan
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2f15d2d13c
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keep developing tileable rr_graph, track2ipin and opin2track to go
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2019-06-19 21:30:16 -06:00 |
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AurelienUoU
|
ff00e4c79c
|
Free only if it's possible to free
|
2019-06-19 16:15:30 -06:00 |
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tangxifan
|
ba15358564
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developing ipin2track mapping for tiles
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2019-06-18 18:06:21 -06:00 |
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tangxifan
|
9ca1b42f4c
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developing switch block pattern for tileable routing architecture
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2019-06-18 16:52:42 -06:00 |
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tangxifan
|
352c97302b
|
start building object GSB graph
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2019-06-17 22:10:30 -06:00 |
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tangxifan
|
f4191315da
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use rr_gsb to build edges of rr_graph
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2019-06-17 18:01:45 -06:00 |
|
tangxifan
|
51ff150a77
|
bug fixing in tileable rr_graph generator
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2019-06-17 10:16:08 -06:00 |
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tangxifan
|
0d14fef53e
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bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator
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2019-06-16 23:02:18 -06:00 |
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tangxifan
|
04ffb99ca6
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-16 16:01:30 -06:00 |
|
Baudouin Chauviere
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57a4ad1f99
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Break memories even in the clb sdc
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2019-06-16 14:27:29 -06:00 |
|
tangxifan
|
1af3b5ef55
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set chan_rr_nodes in tileable rr_graph builder
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2019-06-16 14:23:19 -06:00 |
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tangxifan
|
8c9cc003ea
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developing routing track rr_node set up in tileable routing architecture
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2019-06-15 18:11:08 -06:00 |
|
Xifan Tang
|
155c8d4924
|
fix CMakeList bug in disabling VPR graphics
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2019-06-15 13:21:25 -06:00 |
|
tangxifan
|
18c355d3ee
|
Merge branch 'multimode_clb' into tileable_routing
Conflicts:
vpr7_x2p/vpr/regression_verilog.sh
|
2019-06-15 12:27:40 -06:00 |
|
tangxifan
|
b9feaf0eeb
|
fix conflicts on the regression.sh
|
2019-06-15 12:26:37 -06:00 |
|
tangxifan
|
d19b470b33
|
Merge branch 'tileable_routing' into multimode_clb
Conflicts:
vpr7_x2p/vpr/regression_verilog.sh
|
2019-06-15 12:25:30 -06:00 |
|
tangxifan
|
c8bf456097
|
bug fixing for memory leaking in allocating pb_rr_graph and power estimation
|
2019-06-15 12:23:36 -06:00 |
|
tangxifan
|
d3296d0975
|
developing tileable rr_graph builder
|
2019-06-14 22:35:42 -06:00 |
|
tangxifan
|
a33627606e
|
developing tileable routing track arrangement
|
2019-06-14 17:35:40 -06:00 |
|
AurelienUoU
|
29dadc51b4
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-14 11:46:02 -06:00 |
|
AurelienUoU
|
c76dbaac33
|
Update regression test avoiding overwritting files
|
2019-06-14 11:44:44 -06:00 |
|
tangxifan
|
4d2a3680be
|
support bus explicit port mapping to standard cells (for BRAMs)
|
2019-06-14 11:09:15 -06:00 |
|
tangxifan
|
0902d1e75a
|
c++ string is not working, use char which is stable
|
2019-06-13 18:38:46 -06:00 |
|
tangxifan
|
5f61cd8876
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
Conflicts:
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
|
2019-06-13 16:32:39 -06:00 |
|
tangxifan
|
af1628abfe
|
use bus port for primitives in Verilog generator
|
2019-06-13 16:26:58 -06:00 |
|
tangxifan
|
dddbbac85c
|
merge from multimode_clb bug fixing
|
2019-06-13 15:59:34 -06:00 |
|
AurelienUoU
|
15b4cc9ecb
|
Error correction in memory generation for pb_types without modes
|
2019-06-13 15:34:25 -06:00 |
|
tangxifan
|
43128ad3f0
|
fix a bug in formal verification port for memory bank configuration circuits
|
2019-06-13 15:33:13 -06:00 |
|
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
|
tangxifan
|
5ae4dec0af
|
fix bugs in CMakeList on enable/disable VPR Graphics
|
2019-06-12 22:48:00 -06:00 |
|
tangxifan
|
1d00e3665b
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:50:40 -06:00 |
|
tangxifan
|
65b5454f3a
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:49:10 -06:00 |
|
tangxifan
|
b359893852
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-11 14:41:36 -06:00 |
|
AurelienUoU
|
bf13c1f731
|
Add a script to create a new file with correct path rather than overwrite the existing
|
2019-06-11 14:28:58 -06:00 |
|
tangxifan
|
7245917b9c
|
fix a bug for iopad SPICE generation
|
2019-06-11 11:43:56 -06:00 |
|
tangxifan
|
1776ae3ec8
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
tangxifan
|
8e3ad675e0
|
use sstream for rr_block verilog writer
|
2019-06-10 16:23:35 -06:00 |
|
tangxifan
|
009e5244d3
|
minor fix on the port direction of configuration peripherals for memory decoders
|
2019-06-10 15:39:35 -06:00 |