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fix conflicts on the regression.sh

This commit is contained in:
tangxifan 2019-06-15 12:26:37 -06:00
parent c8bf456097
commit b9feaf0eeb
1 changed files with 0 additions and 1 deletions
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vpr7_x2p/vpr/regression_verilog.sh
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@ -31,6 +31,5 @@ perl arch_rewrite.pl -i $template_arch_xml_file -o $arch_xml_file
cd -
# Run VPR
#valgrind
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy