Tim 'mithro' Ansell
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19aa261527
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Adding COPYING file with license information.
This allows GitHub and other tools to detect the license info. Providing
a COPYING for LICENSE file is also pretty standard.
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2017-10-19 20:22:12 -04:00 |
Clifford Wolf
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716dbc9274
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Revert 90be0d8 as it causes endless loops for some designs
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2017-10-14 11:57:25 +02:00 |
Clifford Wolf
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1954c78ea7
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Add "verific -vlog-libdir"
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2017-10-13 20:23:19 +02:00 |
Clifford Wolf
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e7a3c47cc7
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Add "verific -vlog-incdir" and "verific -vlog-define"
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2017-10-13 20:12:51 +02:00 |
Clifford Wolf
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05068af880
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Update Verific README
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2017-10-13 17:11:53 +02:00 |
Clifford Wolf
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d565bc4a82
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Merge pull request #434 from Kmanfi/vector_fix
Fix input vector for reduce cells.
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2017-10-12 12:16:47 +02:00 |
Kaj Tuomi
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90be0d800b
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Fix input vector for reduce cells.
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2017-10-12 13:05:10 +03:00 |
Clifford Wolf
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bc5cc4e103
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Add Verific fairness/liveness support
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2017-10-12 12:00:09 +02:00 |
Clifford Wolf
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2b03a73a46
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Update ABC to hg rev 6283c5d99b06
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2017-10-11 13:58:51 +02:00 |
Clifford Wolf
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12c10892e6
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-10-10 15:16:45 +02:00 |
Clifford Wolf
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c10e96c9ec
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Start work on pre-processor for Verific SVA properties
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2017-10-10 15:16:39 +02:00 |
Clifford Wolf
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7c57d8fbb4
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Rewrite ABC output to include proper net names in timing report
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2017-10-10 13:32:58 +02:00 |
Clifford Wolf
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142f4ca03a
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Add timing constraints to osu035 example
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2017-10-10 13:32:04 +02:00 |
Clifford Wolf
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bc80426d45
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Remove some dead code
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2017-10-10 12:00:48 +02:00 |
Clifford Wolf
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caa78388cd
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Allow $past, $stable, $rose, $fell in $global_clock blocks
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2017-10-10 11:59:32 +02:00 |
Clifford Wolf
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adf1754729
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Add $shiftx support to verilog front-end
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2017-10-07 13:40:54 +02:00 |
Clifford Wolf
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2b04e8caa6
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Update ABC to hg rev 0fc1803a77c0
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2017-10-06 10:07:33 +02:00 |
Larry Doolittle
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50bcd9a728
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Clean whitespace and permissions in techlibs/intel
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2017-10-05 16:23:49 +02:00 |
Clifford Wolf
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fc3378916d
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Improve handling of Verific errors
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2017-10-05 14:38:32 +02:00 |
Clifford Wolf
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ee56a887b6
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Improve Verific error handling, check VHDL static asserts
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2017-10-04 18:56:28 +02:00 |
Clifford Wolf
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3f22f48eeb
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Add blackbox command
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2017-10-04 18:30:42 +02:00 |
Clifford Wolf
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b92ff2706e
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Fix nasty bug in Verific bindings
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2017-10-04 17:23:42 +02:00 |
Clifford Wolf
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a381188b92
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Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys
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2017-10-03 18:23:45 +02:00 |
Clifford Wolf
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983479f395
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Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys
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2017-10-03 18:20:08 +02:00 |
Clifford Wolf
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b4fd7ecd83
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Merge branch 'dh73-master'
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2017-10-03 17:33:43 +02:00 |
Clifford Wolf
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65f91e5120
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Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
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2017-10-03 17:31:21 +02:00 |
dh73
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4718e65763
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Tested and working altsyncarm without init files
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2017-10-01 19:59:45 -05:00 |
dh73
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e480847753
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Fixed wrong declaration in Verilog backend
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2017-10-01 11:11:32 -05:00 |
dh73
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cbaba62401
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Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
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2017-10-01 11:04:17 -05:00 |
Udi Finkelstein
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eb40278a16
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Turned a few member functions into const, esp. dumpAst(), dumpVlog().
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2017-09-30 07:37:38 +03:00 |
Udi Finkelstein
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72a08eca3d
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Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution
(Oreilly 'Flex & Bison' page 189)
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2017-09-30 06:39:07 +03:00 |
Clifford Wolf
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c5b204d8d2
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Add first draft of eASIC back-end
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2017-09-29 17:53:43 +02:00 |
Clifford Wolf
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e64b9d5a4d
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Fix synth_ice40 doc regarding -top default
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2017-09-29 17:52:57 +02:00 |
Clifford Wolf
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dbfd8460a9
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Allow $size and $bits in verilog mode, actually check test case
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2017-09-29 11:56:43 +02:00 |
Clifford Wolf
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637a02eb5c
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Merge pull request #425 from udif/udif_dollar_bits
Add $bits() and $size()
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2017-09-29 11:39:36 +02:00 |
Clifford Wolf
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29f8acf095
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Merge pull request #421 from stephengroat/osx-travis
Add osx tests using brew bundle
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2017-09-28 14:45:47 +02:00 |
Stephen
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57b3c34e69
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delete bad backslash
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2017-09-27 16:52:20 -07:00 |
Stephen
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1ba06cefcc
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forgot to install bundles
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2017-09-27 16:51:50 -07:00 |
Stephen Groat
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de0797f073
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Add osx tests using brew bundle
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2017-09-27 16:49:03 -07:00 |
Clifford Wolf
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30396270a2
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Increase maximum LUT size in blifparse to 12 bits
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2017-09-27 15:27:42 +02:00 |
Udi Finkelstein
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e951ac0dfb
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$size() now works correctly for all cases!
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
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2017-09-26 20:34:24 +03:00 |
Udi Finkelstein
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6ddc6a7af4
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$size() seems to work now with or without the optional parameter.
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
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2017-09-26 19:18:25 +03:00 |
Clifford Wolf
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91d9c50bb3
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Parse reals as string in JSON front-end
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2017-09-26 14:37:03 +02:00 |
Clifford Wolf
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660473a485
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Merge branch 'vlogpp-inc-fixes'
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2017-09-26 14:02:57 +02:00 |
Clifford Wolf
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2c04d883b1
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Minor coding style fix
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2017-09-26 13:50:14 +02:00 |
Clifford Wolf
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cb1d439d10
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Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master
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2017-09-26 13:48:13 +02:00 |
Udi Finkelstein
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7e391ba904
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enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog
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2017-09-26 09:19:56 +03:00 |
Udi Finkelstein
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2dea42e903
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Added $bits() for memories as well.
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2017-09-26 09:11:25 +03:00 |
Udi Finkelstein
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17f8b41605
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$size() now works with memories as well!
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2017-09-26 08:36:45 +03:00 |
Udi Finkelstein
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64eb8f29ad
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Add $size() function. At the moment it works only on expressions, not on memories.
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2017-09-26 06:25:42 +03:00 |