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Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys

This commit is contained in:
Clifford Wolf 2017-10-03 18:20:08 +02:00
parent b4fd7ecd83 72a08eca3d
commit 983479f395
1 changed files with 5 additions and 3 deletions
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8
frontends/verilog/verilog_parser.y
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@ -142,7 +142,9 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%define parse.error verbose
%define parse.lac full
%expect 2
%nonassoc FAKE_THEN
%nonassoc TOK_ELSE
%debug
%%
@ -1261,7 +1263,7 @@ optional_else:
ast_stack.back()->children.push_back(cond);
ast_stack.push_back(block);
} behavioral_stmt |
/* empty */;
/* empty */ %prec FAKE_THEN;
case_body:
case_body case_item |
@ -1432,7 +1434,7 @@ gen_stmt_or_null:
gen_stmt_block | ';';
opt_gen_else:
TOK_ELSE gen_stmt_or_null | /* empty */;
TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
expr:
basic_expr {