riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,006 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

4006 Commits

Author SHA1 Message Date
Tim 'mithro' Ansell b24b600287 travis: Print branches before fetching, try both locations. 2017-11-25 20:55:39 -08:00
Tim 'mithro' Ansell 1b231b442c minisat: Make update script executable. 2017-11-25 19:48:26 -08:00
Tim 'mithro' Ansell 34c9fbab53 minisat: Only define __STDC_XXX_MACROS if not already defined. 
Replace;
 #define __STDC_LIMIT_MACROS
 #define __STDC_FORMAT_MACROS

With
 #ifndef __STDC_LIMIT_MACROS
 #define __STDC_LIMIT_MACROS
 #endif
 #ifndef __STDC_FORMAT_MACROS
 #define __STDC_FORMAT_MACROS
 #endif

This fixes a compile warning if you are defining these macros in your
CXXFLAGS (as some distros do).
 2017-11-25 19:48:26 -08:00
Tim 'mithro' Ansell 8d48b47450 minisat: Remove template with gzFile specialization. 
All the other gzFile functions have been removed but this template was
still left around.
 2017-11-25 19:48:26 -08:00
Tim 'mithro' Ansell 04802e93e8 subcircuit: Class with virtual methods should have virtual destructor. 
Fixes a compile warning.

* https://stackoverflow.com/questions/1123044/when-should-your-destructor-be-virtual
 2017-11-25 19:48:26 -08:00
Clifford Wolf 66f2d10822 Merge branch 'master' into btor-ng 2017-11-24 18:14:53 +01:00
Clifford Wolf e3a51b3e87 Bugfixes in new BTOR back-end 2017-11-24 18:13:41 +01:00
Clifford Wolf 203c2dae3c
Merge pull request #446 from mithro/travis-rework 
Reworking the Travis CI for Yosys.
 2017-11-24 06:49:15 +01:00
Tim 'mithro' Ansell bc8d40aa88 travis: Use the cache. 2017-11-24 15:45:45 +11:00
Tim 'mithro' Ansell 48fdabdcda travis: Adding gcc-4.8 and gcc-6 on Linux. 2017-11-24 15:45:45 +11:00
Tim 'mithro' Ansell d2850b5b80 travis: Reworking travis setup. 
* Move the code into scripts inside .travis directory.
 * Build on multiple compiler versions.

Fixes #442 - Make travis build pass
Fixes #441 - Fix git version information on travis build
Fixes #440 - Make travis cache the iverilog build
 2017-11-24 15:45:45 +11:00
Clifford Wolf 60d1129506 Progress in new BTOR back-end 2017-11-23 23:44:39 +01:00
Clifford Wolf b3d6b277ea Progress in new BTOR back-end 2017-11-23 18:50:10 +01:00
Clifford Wolf cc2495d48d Progress in new BTOR back-end 2017-11-23 18:14:53 +01:00
Clifford Wolf 388e7a7740 Merge branch 'master' into btor-ng 2017-11-23 09:00:22 +01:00
Clifford Wolf 494a6f7949 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-11-23 08:57:55 +01:00
Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis) 2017-11-23 08:51:38 +01:00
Clifford Wolf e41dcaa759 Progress with new BTOR backend 2017-11-23 08:28:29 +01:00
Clifford Wolf 6ee305553a Add skeleton for new BTOR back-end 2017-11-23 06:38:57 +01:00
Clifford Wolf eceacdb9a3 Remove old BTOR back-end 2017-11-23 04:28:51 +01:00
Clifford Wolf 4782d59a3f
Merge pull request #455 from daveshah1/up5k 
Add UltraPlus specific cells to ice40 techlib
 2017-11-18 19:12:48 +01:00
David Shah 0505f1043c Remove unnecessary keep attributes 2017-11-18 17:53:21 +00:00
Clifford Wolf 5b6e52118c Accept real-valued delay values 2017-11-18 10:01:30 +01:00
Clifford Wolf a4195e83c7
Merge pull request #452 from cr1901/master 
Accommodate Windows-style paths during include-file processing.
 2017-11-18 09:58:40 +01:00
Clifford Wolf c01df04e32
Merge pull request #453 from dh73/master 
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
 2017-11-18 09:56:36 +01:00
David Shah 8ae73e60e2 Merge branch 'master' into up5k 2017-11-17 15:15:39 +00:00
Clifford Wolf 234726c655 Add "synth_ice40 -vpr" 2017-11-16 21:37:02 +01:00
David Shah f9f3ca5da0 Add some UltraPlus cells to ice40 techlib 2017-11-16 12:24:35 +00:00
dh73 acee813a5c Fixed the -vout flag to -vqm in examples/intel directory 2017-11-14 22:55:48 -06:00
William D. Jones abc5b4b8ce Accommodate Windows-style paths during include-file processing. 2017-11-14 16:16:24 -05:00
dh73 3fd1d61e2a Initial Cyclone 10 support 2017-11-08 22:45:21 -06:00
dh73 cf8cc50bf5 Merge https://github.com/cliffordwolf/yosys 2017-11-08 20:24:01 -06:00
dh73 1fc061d90c Organizing Speedster file names 2017-11-08 20:23:55 -06:00
Clifford Wolf 9ae25039fb Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
Clifford Wolf 4f31cb6dad Add "ltp" command 2017-10-31 12:40:25 +01:00
Clifford Wolf 455c1c9d97 Fix SMT2 handling of initstate in sub-modules 2017-10-29 13:21:20 +01:00
Clifford Wolf c238f45ecf Fix memory corruption bug in opt_rmdff 2017-10-26 18:02:15 +02:00
Clifford Wolf 1e502ef5a0 Fix typo in opt_clean log message 2017-10-26 18:01:48 +02:00
Clifford Wolf 1170508264 Improve smtio performance by using reader thread, not writer thread 2017-10-26 01:01:55 +02:00
Clifford Wolf f513494f5f Use separate writer thread for talking to SMT solver to avoid read/write deadlock 2017-10-25 19:59:56 +02:00
Clifford Wolf 76326c163a Improve p_* functions in smtio.py 2017-10-25 15:45:32 +02:00
Clifford Wolf 104b9dc96b Disable OSX in .travis.yml 2017-10-25 15:17:29 +02:00
Clifford Wolf 9a038861c8 Add ENABLE_DEBUG config flag 2017-10-25 14:57:16 +02:00
Clifford Wolf af36755e0a Update ABC to hg rev f6838749f234 2017-10-25 14:51:59 +02:00
Clifford Wolf a8cf431d9c Remove vhdl2verilog 2017-10-25 14:50:22 +02:00
Clifford Wolf c672c321e3 Capsulate smt-solver read/write in separate functions 2017-10-25 13:37:11 +02:00
Clifford Wolf dd46d76394 Fix a bug in yosys-smtbmc in ROM handling 2017-10-25 13:05:14 +02:00
Clifford Wolf baddb017fe Remove PSL example from tests/sva/ 2017-10-20 13:16:24 +02:00
Clifford Wolf 0a31a0b3ae Remove all PSL support code from verific.cc 2017-10-20 13:14:04 +02:00
Clifford Wolf 309f8fe74f Merge pull request #437 from mithro/master 
Adding COPYING file with license information.
 2017-10-20 11:44:54 +02:00