riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,463 Commits 114 Branches 50 Tags 34 MiB
Commit Graph

832 Commits

Author SHA1 Message Date
Eddie Hung 727eec04c5 Refactor synth_xilinx to auto-generate doc 2019-04-26 14:32:18 -07:00
Eddie Hung 1ea6d7920f Cleanup ice40 2019-04-26 14:31:59 -07:00
Eddie Hung f14d7f0df6 Cleanup superseded 2019-04-25 19:43:41 -07:00
Eddie Hung 019c48b508 bitblast_shiftx -> split_shiftx 2019-04-25 19:38:35 -07:00
Eddie Hung feff976454 synth_xilinx to call bitblast_shiftx 2019-04-25 17:11:18 -07:00
Eddie Hung f96d82a5f1 Add -nocarry option to synth_xilinx 2019-04-24 16:46:41 -07:00
Clifford Wolf 64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00
Clifford Wolf 4575e4ad86 Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:18:04 +02:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf a7e11261bd Add $specify2 and $specify3 cells to simlib 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Eddie Hung 60026842b2 Tweak 2019-04-22 17:59:56 -07:00
Eddie Hung 26e461f47d Fix for A_WIDTH == 2 but B_WIDTH==3 2019-04-22 17:58:28 -07:00
Eddie Hung 1fa2c36fbd Trim A_WIDTH by Y_WIDTH-1 2019-04-22 17:14:11 -07:00
Eddie Hung 69863f7698 Add comment 2019-04-22 16:58:44 -07:00
Eddie Hung 61161faefc Fix for mux_case_* mappings 2019-04-22 16:56:18 -07:00
Eddie Hung ac1e13819e Fix for non-pow2 width muxes 2019-04-22 14:26:13 -07:00
Eddie Hung 75b96b1aff Add synth_xilinx -nomux option 2019-04-22 12:36:15 -07:00
Eddie Hung 79fb291dbe Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
Eddie Hung 4cfef7897f Merge branch 'xaig' into xc7mux 2019-04-22 11:58:59 -07:00
Eddie Hung 4486a98fd5 Merge remote-tracking branch 'origin/xc7srl' into xc7mux 2019-04-22 11:45:49 -07:00
Eddie Hung ec88129a5c Update help message 2019-04-22 11:38:23 -07:00
Eddie Hung 4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Eddie Hung 0e76718720 Move 'shregmap -tech xilinx' into map_cells 2019-04-22 10:45:39 -07:00
Eddie Hung e300b1922c Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-22 10:36:27 -07:00
Clifford Wolf 0e7901e45c
Merge pull request #941 from Wren6991/sim_lib_io_clke 
ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
 2019-04-22 09:11:13 +02:00
Clifford Wolf 913659d644 Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
Clifford Wolf cf1ba46fa0 Re-added clean after techmap in synth_xilinx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 09:03:11 +02:00
Clifford Wolf cbd9b8a3f3
Merge pull request #916 from YosysHQ/map_cells_before_map_luts 
synth_xilinx to map_cells before map_luts
 2019-04-22 09:01:00 +02:00
Clifford Wolf 19fd411e77
Merge pull request #911 from mmicko/gowin-nobram 
Make nobram false by default for gowin
 2019-04-22 08:58:09 +02:00
Eddie Hung d342b5b135 Tidy up, fix for -nosrl 2019-04-21 15:33:03 -07:00
Eddie Hung d7f0700bae Convert to use #945 2019-04-21 15:19:02 -07:00
Eddie Hung 726e2da8f2 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-21 14:28:55 -07:00
Eddie Hung a3371e118b Merge branch 'master' into map_cells_before_map_luts 2019-04-21 14:24:50 -07:00
Eddie Hung ae95aba60a Add comments 2019-04-21 14:16:59 -07:00
Eddie Hung d99422411f Use new pmux2shiftx from #944, remove my old attempt 2019-04-21 14:16:34 -07:00
Luke Wren 71da836300 ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments 2019-04-21 21:40:11 +01:00
Eddie Hung caec7f9d2c Merge remote-tracking branch 'origin/master' into xaig 2019-04-20 12:23:49 -07:00
Eddie Hung 13ad19482f Merge remote-tracking branch 'origin' into xc7srl 2019-04-20 10:41:43 -07:00
Eddie Hung af4652522f ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set 2019-04-19 21:09:55 -07:00
Eddie Hung 2776925bcf Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
Eddie Hung 19b660ff6e Fix SB_DFF comb model 2019-04-18 23:07:16 -07:00
Eddie Hung 0919f36b88 Missing close bracket 2019-04-18 17:50:11 -07:00
Eddie Hung cf66416110 Annotate SB_DFF* with abc_flop and abc_box_id 2019-04-18 17:46:53 -07:00
Eddie Hung ca1eb98a97 Add SB_DFF* to boxes 2019-04-18 17:46:32 -07:00
Eddie Hung 4c327cf316 Use new -wb flag for ABC flow 2019-04-18 10:32:41 -07:00
Eddie Hung 9278192efe Also update Makefile.inc 2019-04-18 09:58:34 -07:00
Eddie Hung 7b6ab937c1 Make SB_LUT4 a blackbox 2019-04-18 09:05:22 -07:00
Eddie Hung 8024f41897 Fix rename 2019-04-18 09:04:34 -07:00
Eddie Hung ed5e75ed7d Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
Eddie Hung 6008bb7002 Revert "synth_* with -retime option now calls abc with -D 1 as well" 
This reverts commit 9a6da9a79a.
 2019-04-18 07:59:16 -07:00
Eddie Hung 0642baabbc Merge branch 'master' into eddie/fix_retime 2019-04-18 07:57:17 -07:00
Eddie Hung 8fd455c910 Update Makefile.inc too 2019-04-17 15:19:48 -07:00
Eddie Hung c795e14d25 Reduce to three devices: hx, lp, u 2019-04-17 15:19:02 -07:00
Eddie Hung 5c0853fc51 Add up5k timings 2019-04-17 15:10:39 -07:00
Eddie Hung 4b520ae627 Fix grammar 2019-04-17 15:10:22 -07:00
Eddie Hung 3105a8a653 Update error message 2019-04-17 15:07:44 -07:00
Eddie Hung 6f3e5297db Add "-device" argument to synth_ice40 2019-04-17 15:04:46 -07:00
Eddie Hung 671cca59a9 Missing abc_flop_q attribute on SPRAM 2019-04-17 14:44:08 -07:00
Eddie Hung 437fec0d88 Map to SB_LUT4 from fastest input first 2019-04-17 13:01:17 -07:00
Eddie Hung 58847df1b9 Mark seq output ports with "abc_flop_q" attr 2019-04-17 12:27:45 -07:00
Eddie Hung 1eade06671 Also update Makefile.inc 2019-04-17 12:27:02 -07:00
Eddie Hung 4fb9ccfcd8 synth_ice40 to use renamed files 2019-04-17 12:22:03 -07:00
Eddie Hung 42c33db22c Rename to abc.* 2019-04-17 12:15:34 -07:00
Eddie Hung c1ebe51a75 Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 
This reverts commit a7632ab332.
 2019-04-17 11:10:20 -07:00
Eddie Hung a7632ab332 Try using an ICE40_CARRY_LUT primitive to avoid ABC issues 2019-04-17 11:10:04 -07:00
Eddie Hung 17fb6c3522 Fix spacing 2019-04-17 08:40:50 -07:00
Eddie Hung 743c164eee Add SB_LUT4 to box library 2019-04-16 17:34:11 -07:00
Eddie Hung 7980118d74 Add ice40 box files 2019-04-16 16:39:30 -07:00
Eddie Hung cbb85e40e8 Add MUXCY and XORCY to cells_box.v 2019-04-16 14:53:28 -07:00
Eddie Hung aece97024d Fix spacing 2019-04-16 13:16:20 -07:00
Eddie Hung 53b19ab1f5 Make cells.box whiteboxes not blackboxes 2019-04-16 12:43:14 -07:00
Eddie Hung 5189695362 read_verilog cells_box.v before techmap 2019-04-16 12:41:56 -07:00
Eddie Hung d259e6dc14 synth_xilinx: before abc read +/xilinx/cells_box.v 2019-04-16 11:21:46 -07:00
Eddie Hung 3ac4977b70 Add +/xilinx/cells_box.v containing models for ABC boxes 2019-04-16 11:21:03 -07:00
Eddie Hung 8c6cf07acf Revert "Add abc_box_id attribute to MUXF7/F8 cells" 
This reverts commit 8fbbd9b129.
 2019-04-16 11:14:59 -07:00
Eddie Hung 8fbbd9b129 Add abc_box_id attribute to MUXF7/F8 cells 2019-04-15 22:25:09 -07:00
Eddie Hung 538592067e Merge branch 'xaig' into xc7mux 2019-04-15 22:04:20 -07:00
Diego f9272fc56d GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
Eddie Hung 04e466d5e4 Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-12 12:28:37 -07:00
Eddie Hung f77da46a87 Merge remote-tracking branch 'origin/master' into xaig 2019-04-12 12:21:48 -07:00
Eddie Hung db1a5ec6a2
Merge pull request #928 from litghost/add_xc7_sim_models 
Add additional cells sim models for core 7-series primitives.
 2019-04-12 11:52:45 -07:00
Eddie Hung 8228b593ef Merge remote-tracking branch 'origin/master' into xc7mux 2019-04-12 09:46:07 -07:00
Keith Rothman 1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-12 09:35:15 -07:00
Diego 643ae9bfc5 Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
Eddie Hung 233edf00fe Fix cells_map.v some more 2019-04-11 10:48:14 -07:00
Eddie Hung 8658b56a08 More fine tuning 2019-04-11 10:08:05 -07:00
Eddie Hung 0ec8564099 Fix cells_map.v 2019-04-11 10:04:58 -07:00
Eddie Hung bca3779657 Fix typo 2019-04-11 09:25:19 -07:00
Eddie Hung 87b8d29a90 Juggle opt calls in synth_xilinx 2019-04-11 09:13:39 -07:00
Eddie Hung cd7b2de27f WIP for cells_map.v -- maybe working? 2019-04-10 18:05:09 -07:00
Eddie Hung 3d577586fd Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 2019-04-10 16:15:23 -07:00
Eddie Hung 3f5dab0d09 Fix for when B_SIGNED = 1 2019-04-10 14:51:10 -07:00
Eddie Hung 32561332b2 Update doc for synth_xilinx 2019-04-10 14:48:58 -07:00
Eddie Hung 17a02df05c ff_map.v after abc 2019-04-10 12:36:06 -07:00
Eddie Hung 1ec949d5ed Tidy up 2019-04-10 09:02:42 -07:00
Eddie Hung 526aef9c2a Move map_cells to before map_luts 2019-04-10 08:50:31 -07:00
Eddie Hung e0b46eb4cb WIP for $shiftx to wide mux 2019-04-10 08:49:55 -07:00
Eddie Hung 4dac9818bd Update LUT delays 2019-04-10 08:49:39 -07:00
Eddie Hung 9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well 2019-04-10 08:32:53 -07:00