riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2,470 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

2470 Commits

Author SHA1 Message Date
Clifford Wolf ad919ae4e3 Fixed techmap processes error msg 2015-07-18 12:16:27 +02:00
Clifford Wolf 54588a276a Avoid tristate warning for blackbox ice40/cells_sim.v 2015-07-18 11:59:04 +02:00
Clifford Wolf 8393f70538 Some fixes in "select" command 2015-07-16 22:10:26 +02:00
Clifford Wolf 55acc51ad4 Fixed YosysJS.create_worker() usage of this.url_prefix 2015-07-10 13:20:57 +02:00
Clifford Wolf 85aaf08e53 Improved liberty file test case 2015-07-06 17:45:56 +02:00
Clifford Wolf 3049a08912 Updated ABC 2015-07-06 17:45:40 +02:00
Clifford Wolf d2ff5d9994 Do not collect disabled $memwr cells 2015-07-06 13:28:00 +02:00
Clifford Wolf c4dde71dca Improved YosysJS WebWorker API 2015-07-04 17:08:44 +02:00
Clifford Wolf 766dd51447 Bugfix in fsm_extract 2015-07-03 18:42:36 +02:00
Clifford Wolf f0c9a099d2 Added "synth -nofsm" 2015-07-02 15:25:38 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 053058d781 Added opt_const -clkinv 2015-07-01 10:49:21 +02:00
Clifford Wolf ee9188a5b4 Added logic-loop error handling to freduce 2015-06-30 17:11:46 +02:00
Clifford Wolf 7987f23200 Merge branch 'master' of github.com:cliffordwolf/yosys 2015-06-30 01:49:55 +02:00
Clifford Wolf 77e89399a6 Bugfix in chparam 2015-06-30 01:38:34 +02:00
Clifford Wolf caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf 358e415918 Added YosysJS.create_worker() 2015-06-28 17:47:58 +02:00
Clifford Wolf df0163cd2b iCE40: set min bram efficiency to 2% 2015-06-20 09:31:19 +02:00
Clifford Wolf 94fbaff58f Using static mem size of 128 MB in emcc build 2015-06-20 08:58:02 +02:00
Clifford Wolf 3123c45415 Added init support to SMV back-end 2015-06-19 16:43:02 +02:00
Clifford Wolf 6c6bf4999e Progress in SMV back-end 2015-06-19 16:26:53 +02:00
Clifford Wolf 8c79765de5 Progress in SMV back-end 2015-06-19 14:08:46 +02:00
Clifford Wolf 8a86162ae9 Progress in SMV back-end 2015-06-18 16:29:11 +02:00
Clifford Wolf 8e84418225 Progress in SMV back-end 2015-06-17 09:56:42 +02:00
Clifford Wolf 99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf 9f7a5b4ef9 Progress in SMV back-end 2015-06-17 07:24:27 +02:00
Clifford Wolf b8c5e27006 Progress in SMV back-end 2015-06-16 19:05:26 +02:00
Clifford Wolf ed128b82d7 Added "synth -nordff -noalumacc" 2015-06-15 17:07:40 +02:00
Clifford Wolf 52315039c5 Progress in SMV back-end 2015-06-15 17:01:01 +02:00
Clifford Wolf 0f01ef61ef Progress in SMV back-end 2015-06-15 13:24:17 +02:00
Clifford Wolf ea23bb8aa4 Added "write_smv" skeleton 2015-06-15 00:46:27 +02:00
Clifford Wolf 93685a77c6 Removed debug code from write_smt2 2015-06-14 16:22:06 +02:00
Clifford Wolf 66910e15b2 Modernized memory_dff (and fixed a bug) 2015-06-14 16:15:51 +02:00
Clifford Wolf f6eca509bb Added "memory -nordff" 2015-06-14 15:47:11 +02:00
Clifford Wolf 255dcb27a0 Added write_smt2 -mem 2015-06-14 15:46:47 +02:00
Clifford Wolf 285f140f60 Makefile fix for YosysJS build 2015-06-11 15:48:40 +02:00
Clifford Wolf 4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf 3a6abc9bf6 Improvements in cellaigs.cc and "json -aig" 2015-06-11 10:48:16 +02:00
Clifford Wolf 1ae360cf72 AigMaker refactoring 2015-06-10 23:00:12 +02:00
Clifford Wolf e534881794 Added "json -aig" 2015-06-10 08:13:56 +02:00
Clifford Wolf 56d4822719 Renamed "aig" to "aigmap" 2015-06-10 07:24:26 +02:00
Clifford Wolf 85287295b2 Fixed cellaigs port extending 2015-06-10 07:16:30 +02:00
Clifford Wolf 66f9ee412a Added "aig" pass 2015-06-09 22:33:26 +02:00
Clifford Wolf 9500b564ac synth_ice40 now flattens by default 2015-06-09 20:28:17 +02:00
Clifford Wolf e49e2662aa Added cellaigs API 2015-06-09 09:54:22 +02:00
Clifford Wolf b57cb4a7fe Merge clock inverters in memory_dff 2015-06-09 07:25:12 +02:00
Clifford Wolf c88be7bae5 Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys 2015-06-09 06:42:07 +02:00
luke whittlesey 2f90499e3d $mem cell in verilog backend : grouped writes by clock 2015-06-08 17:35:40 -04:00
Clifford Wolf de4f4dad3c Fixed "avail_parameters" handling in module clone/copy 2015-06-08 14:49:34 +02:00
Clifford Wolf 98650a0609 Added log_dump() support for IdStrings 2015-06-08 14:49:02 +02:00