Clifford Wolf
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e122c2644e
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preserve used $-wires with init attribute in opt_clean
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2015-05-22 08:20:29 +02:00 |
Clifford Wolf
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4744bb95fb
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Some fixes for $mem in verilog back-end
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2015-05-20 13:55:50 +02:00 |
Clifford Wolf
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6061b7bd58
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bugfix in blif front-end
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2015-05-18 11:15:49 +02:00 |
Clifford Wolf
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83499dc1ba
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added vloghtb test_febe.sh
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2015-05-17 19:54:00 +02:00 |
Clifford Wolf
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3ecb2bf067
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Improved .latch support in BLIF front-end
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2015-05-17 18:58:24 +02:00 |
Clifford Wolf
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2cc4e75914
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Added read_blif command
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2015-05-17 15:25:03 +02:00 |
Clifford Wolf
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e5116eeb77
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Generalized blifparse API
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2015-05-17 15:10:37 +02:00 |
Clifford Wolf
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7dad017c9c
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abc/blifparse files reorganization
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2015-05-17 14:44:28 +02:00 |
Clifford Wolf
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61512b6f41
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Verific build fixes
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2015-05-17 08:19:52 +02:00 |
Clifford Wolf
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c2f30e0de4
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Added .barbuf support to abc BLIF parser
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2015-05-13 06:45:12 +02:00 |
Clifford Wolf
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dae00e1d83
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changed file() to open() in python scripts
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2015-05-11 21:58:21 +02:00 |
Clifford Wolf
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42348cddd9
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Merge pull request #63 from wluker/verilog-backend-mem
Fixed bug in $mem cell verilog code generation.
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2015-05-11 21:38:06 +02:00 |
luke whittlesey
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3bb5f064b8
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Fixed bug in $mem cell verilog code generation.
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2015-05-11 14:05:18 -04:00 |
Clifford Wolf
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9e56739634
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Disabled broken $mem support in verilog backend
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2015-05-10 21:38:41 +02:00 |
Clifford Wolf
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e47218e9ea
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Merge pull request #62 from wluker/verilog-backend-mem
Added support for $mem cells in the verilog backend.
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2015-05-10 21:23:59 +02:00 |
luke whittlesey
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6de8fea2c7
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Made changes recommended by Clifford Wolf ...
Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
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2015-05-10 11:33:24 -04:00 |
luke whittlesey
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2c1e150297
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Verilog backend for $mem cells should now be able to handle different
write-enable bits and RD_TRANSPARENT parameter settings.
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2015-05-08 15:29:51 -04:00 |
luke whittlesey
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c0b68f4848
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Added support for $mem cells in the verilog backend.
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2015-05-07 13:03:09 -04:00 |
eddiehung
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7c62318239
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Fix for all zero mask
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2015-05-03 12:53:09 +01:00 |
eddiehung
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079c1205fe
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Escape '<' and '>' some more
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2015-05-03 10:37:20 +01:00 |
Clifford Wolf
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7462618591
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Fixed memory_unpack for initialized memories
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2015-04-29 19:55:32 +02:00 |
Clifford Wolf
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96be31de89
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Preserve important attributes in splitnets
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2015-04-29 07:44:57 +02:00 |
Clifford Wolf
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f483dce7c2
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Added $eq/$neq -> $logic_not/$reduce_bool optimization
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2015-04-29 07:28:15 +02:00 |
eddiehung
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872e13321c
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For vtr, escape angle brackets as well
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2015-04-28 08:56:00 +01:00 |
eddiehung
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058deb777e
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blifwriter: write out .names for true/false/undef type == '-'
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2015-04-28 08:55:26 +01:00 |
Clifford Wolf
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9d067fecea
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ice40_opt bugfix
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2015-04-27 11:36:13 +02:00 |
Clifford Wolf
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310fde197e
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iCE40: SB_CARRY const fold -> unmap SB_LUT
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2015-04-27 10:27:50 +02:00 |
Clifford Wolf
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794d22969d
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Added simplemap $lut support
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2015-04-27 10:16:07 +02:00 |
Clifford Wolf
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8d4a675f91
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Added iCE40 const folding support for SB_CARRY
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2015-04-27 08:38:14 +02:00 |
Clifford Wolf
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752851954b
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Initialization support for all iCE40 bram modes
|
2015-04-26 08:39:31 +02:00 |
Clifford Wolf
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b4d7a590e8
|
initialized iCE40 brams (mode 0)
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2015-04-25 20:44:51 +02:00 |
Clifford Wolf
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4cc4400514
|
improved iCE40 SB_RAM40_4K simulation model
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2015-04-25 20:01:37 +02:00 |
Clifford Wolf
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bd0597137d
|
Updated ABC to hg rev 779de2de1481
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2015-04-25 18:07:13 +02:00 |
Clifford Wolf
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82a4722f46
|
More iCE40 bram improvements
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2015-04-25 18:04:57 +02:00 |
Clifford Wolf
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49859393bb
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Improved attributes API and handling of "src" attributes
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2015-04-24 22:04:05 +02:00 |
Clifford Wolf
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687f5a5b12
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iCE40 bram progress
|
2015-04-24 15:38:11 +02:00 |
Clifford Wolf
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308a59aa18
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iCE40 bram tests and fixes
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2015-04-24 08:32:07 +02:00 |
Clifford Wolf
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d6f7698f59
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Added ice40 bram support
|
2015-04-24 00:06:50 +02:00 |
Clifford Wolf
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11f77205f5
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Fixed memory_share for unconditional write with part select to memory
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2015-04-22 06:40:23 +02:00 |
Clifford Wolf
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1277d1bcb8
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iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
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2015-04-19 21:37:40 +02:00 |
Clifford Wolf
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7ff802e199
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Verilog front-end: define `BLACKBOX in -lib mode
|
2015-04-19 21:30:46 +02:00 |
Clifford Wolf
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49ef830464
|
added sync reset to ice40 test_ffs.sh
|
2015-04-18 09:41:31 +02:00 |
Clifford Wolf
|
f564a65851
|
Added ice40 test_arith
|
2015-04-18 09:33:34 +02:00 |
Clifford Wolf
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f78fa718be
|
Added ice40 SB_CARRY support
|
2015-04-18 09:33:08 +02:00 |
Clifford Wolf
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faa95dd845
|
don't consider blackbox modules in "sat" command
|
2015-04-18 09:29:03 +02:00 |
Clifford Wolf
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9041f34233
|
Improved handling of init values in opt_rmdff
based on a patch by Mingyu Gao, user gaomy3832 on github
|
2015-04-18 08:04:31 +02:00 |
Clifford Wolf
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8cdbcf6859
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Bugfix for $_DFF_?_ in "dff2dffe -direct-match"
|
2015-04-17 21:35:59 +02:00 |
Clifford Wolf
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661b647559
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Added mapping of synchronous set/reset to iCE40 flow
|
2015-04-17 11:54:25 +02:00 |
Clifford Wolf
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e050467b89
|
Improved "maccmap" help message
|
2015-04-16 18:23:43 +02:00 |
Clifford Wolf
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cfdc9fc50e
|
A "#" does start a comment, not a label.
|
2015-04-16 18:13:41 +02:00 |