Clifford Wolf
31755ed1cf
Changed ice40 ICESTORM_CARRYCONST port name
2015-04-16 12:09:14 +02:00
Clifford Wolf
dc30b034f7
Fixed "dff2dffe -direct-match"
2015-04-16 11:47:59 +02:00
Clifford Wolf
3e9e6e1c22
Added simple ice40 dff tests
2015-04-16 11:31:15 +02:00
Clifford Wolf
0d344a23d3
improved ice40 dff cell mapping
2015-04-16 11:30:56 +02:00
Clifford Wolf
f80d020f17
Added "dff2dffe -direct-match"
2015-04-16 11:30:17 +02:00
Clifford Wolf
4529c56cc6
use "hierarchy -auto-top" in synth_ice40
2015-04-14 13:45:15 +02:00
Clifford Wolf
06ce496f8d
more cells in ice40 cell library
2015-04-14 13:44:43 +02:00
Clifford Wolf
2fc2f8f5b3
Added "splice -wires"
2015-04-13 19:28:12 +02:00
Clifford Wolf
e305d85807
Added handling of bool-output cells to "wreduce"
2015-04-13 19:27:49 +02:00
Clifford Wolf
3481f46d1e
Improved xilinx "bram1" test
2015-04-09 17:12:12 +02:00
Clifford Wolf
7319951145
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
Clifford Wolf
44519d4399
Added back-end auto-detect for .edif and .json
2015-04-09 15:37:54 +02:00
Clifford Wolf
d176e613c2
Minor fixes in handling of "init" attribute
2015-04-09 15:12:26 +02:00
Clifford Wolf
229825e1b8
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 13:37:07 +02:00
Clifford Wolf
25781e329b
Fixed const2big performance bug
2015-04-09 13:20:19 +02:00
Clifford Wolf
be7b9b34ca
techmap code cleanup
2015-04-09 12:02:26 +02:00
Clifford Wolf
b00cad81d7
Towards DRAM support in Xilinx flow
2015-04-09 08:17:14 +02:00
Clifford Wolf
21a1cc1b60
Added support for "file names with blanks"
2015-04-08 12:14:34 +02:00
Clifford Wolf
aa0ab975b9
Removed "techmap -share_map" (use "-map +/filename" instead)
2015-04-08 12:13:53 +02:00
Clifford Wolf
8eadd8fb18
Added %M and %C select operators
2015-04-07 22:22:09 +02:00
Clifford Wolf
724cead61d
Added "pmuxtree" command
2015-04-07 20:27:10 +02:00
Clifford Wolf
1f33b2a490
Added "chparam -list"
2015-04-07 19:21:30 +02:00
Clifford Wolf
590f74d8f0
Added decoder generation to "muxcover"
2015-04-07 18:03:27 +02:00
Clifford Wolf
aae5f2ca08
Added hashlib support for std::tuple<>
2015-04-07 17:23:30 +02:00
Clifford Wolf
f7fb21f185
Added "muxcover" command
2015-04-07 15:42:25 +02:00
Clifford Wolf
b31e77fd06
Added pool<K>::pop()
2015-04-07 15:07:01 +02:00
Clifford Wolf
c1af590f4e
typo fix
2015-04-07 07:43:01 +02:00
Clifford Wolf
329b841aac
Added "chparam" command
2015-04-07 07:30:14 +02:00
Clifford Wolf
8520b7fbe0
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
Clifford Wolf
169d1c4711
Added support for initialized brams
2015-04-06 17:06:15 +02:00
Clifford Wolf
d19866615b
Added Xilinx test case for initialized brams
2015-04-06 13:27:11 +02:00
Clifford Wolf
4389d9306e
Added Xilinx bram black-box modules
2015-04-06 08:44:30 +02:00
Clifford Wolf
c0e2b3eb11
Added "port_directions" to write_json output
2015-04-06 01:49:58 +02:00
Clifford Wolf
a1c62b79d5
Avoid parameter values with size 0 ($mem cells)
2015-04-05 18:04:19 +02:00
Clifford Wolf
95944eb69e
make all vector-size related integer params in $mem sim model signed
...
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
2015-04-05 17:26:53 +02:00
Clifford Wolf
706631225e
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-05 09:45:14 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
b0c0ede879
Added "init" attribute support to verilog backend
2015-04-04 18:06:52 +02:00
Clifford Wolf
0737bf5fb8
appnote 012 fix
2015-04-04 15:13:35 +02:00
Clifford Wolf
1d5d1f79f9
Appnote 012
2015-04-04 14:52:25 +02:00
Clifford Wolf
082550f1f3
Updated ABC to 51705b168d7a
2015-04-04 11:47:59 +02:00
Clifford Wolf
3b6ebb62fc
Merge pull request #55 from ahmedirfan1983/master
...
added appnote and impr in btor
2015-04-04 09:35:21 +02:00
Ahmed Irfan
13e2e71ebe
Update README
...
corrected url
2015-04-03 17:11:45 +02:00
Ahmed Irfan
ed750f0a55
Delete btor.ys
...
.ys script not needed
2015-04-03 16:45:54 +02:00
Ahmed Irfan
e82e4f7df4
Update README
...
pmux cell is implemented
2015-04-03 16:45:14 +02:00
Ahmed Irfan
ea2e0297d5
separated memory next from write cell
2015-04-03 16:41:50 +02:00
Ahmed Irfan
bdf6b2b19a
Merge branch 'master' of https://github.com/cliffordwolf/yosys
2015-04-03 16:38:07 +02:00
Ahmed Irfan
8acdd90bc9
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor
2015-04-03 16:34:05 +02:00
Ahmed Irfan
7ad179151b
appnote for verilog to btor
2015-04-03 16:20:29 +02:00
Clifford Wolf
4b44907619
documentation improvements
2015-03-29 20:22:08 +02:00