mirror of https://github.com/YosysHQ/yosys.git
Fixed const2big performance bug
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@ -41,21 +41,28 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
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static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
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{
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BigInteger result = 0, this_bit = 1;
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for (size_t i = 0; i < val.bits.size(); i++) {
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if (val.bits[i] == RTLIL::State::S1) {
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if (as_signed && i+1 == val.bits.size())
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result -= this_bit;
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else
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result += this_bit;
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}
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else if (val.bits[i] != RTLIL::State::S0) {
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if (undef_bit_pos < 0)
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undef_bit_pos = i;
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}
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this_bit *= 2;
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BigUnsigned mag;
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BigInteger::Sign sign = BigInteger::positive;
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State inv_sign_bit = RTLIL::State::S1;
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size_t num_bits = val.bits.size();
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if (as_signed && num_bits && val.bits[num_bits-1] == RTLIL::State::S1) {
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inv_sign_bit = RTLIL::State::S0;
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sign = BigInteger::negative;
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num_bits--;
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}
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return result;
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for (size_t i = 0; i < num_bits; i++)
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if (val.bits[i] == RTLIL::State::S0 || val.bits[i] == RTLIL::State::S1)
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mag.setBit(i, val.bits[i] == inv_sign_bit);
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else if (undef_bit_pos < 0)
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undef_bit_pos = i;
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if (sign == BigInteger::negative)
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mag += 1;
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return BigInteger(mag, sign);
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}
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static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos)
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