mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #55 from ahmedirfan1983/master
added appnote and impr in btor
This commit is contained in:
Clifford Wolf
commit
3b6ebb62fc
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@ -3,7 +3,7 @@ This is the Yosys BTOR backend.
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It is developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy
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Master git repository for the BTOR backend:
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https://github.com/ahmedirfan1983/yosys/tree/btor
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https://github.com/ahmedirfan1983/yosys
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[[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking
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@ -19,5 +19,5 @@ Todos:
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- async resets
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- etc..
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- Add support for $pmux and $lut cells
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- Add support for $lut cells
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@ -78,7 +78,7 @@ struct BtorDumper
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std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers
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RTLIL::IdString curr_cell; //current cell being dumped
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std::map<std::string, std::string> cell_type_translation, s_cell_type_translation; //RTLIL to BTOR translation
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std::set<int> mem_next; //if memory (line_number) already has next
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std::map<int, std::set<std::pair<int,int>>> mem_next; // memory (line_number)'s set of condition and write
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BtorDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
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f(f), module(module), design(design), config(config), ct(design), sigmap(module)
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{
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@ -269,6 +269,45 @@ struct BtorDumper
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else return it->second;
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}
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int dump_memory_next(const RTLIL::Memory* memory)
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{
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auto mem_it = line_ref.find(memory->name);
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int address_bits = ceil(log(memory->size)/log(2));
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if(mem_it==std::end(line_ref))
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{
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log("can not write next of a memory that is not dumped yet\n");
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log_abort();
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}
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else
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{
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auto acond_list_it = mem_next.find(mem_it->second);
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if(acond_list_it!=std::end(mem_next))
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{
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std::set<std::pair<int,int>>& cond_list = acond_list_it->second;
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if(cond_list.empty())
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{
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return 0;
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}
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auto it=cond_list.begin();
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++line_num;
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str = stringf("%d acond %d %d %d %d %d", line_num, memory->width, address_bits, it->first, it->second, mem_it->second);
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f << stringf("%s\n", str.c_str());
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++it;
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for(; it!=cond_list.end(); ++it)
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{
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++line_num;
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str = stringf("%d acond %d %d %d %d %d", line_num, memory->width, address_bits, it->first, it->second, line_num-1);
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f << stringf("%s\n", str.c_str());
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}
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++line_num;
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str = stringf("%d anext %d %d %d %d", line_num, memory->width, address_bits, mem_it->second, line_num-1);
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f << stringf("%s\n", str.c_str());
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return 1;
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}
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return 0;
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}
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}
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int dump_const(const RTLIL::Const* data, int width, int offset)
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{
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log("writing const \n");
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@ -775,7 +814,8 @@ struct BtorDumper
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str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
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int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
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//check if the memory has already next
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auto it = mem_next.find(mem);
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/*
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auto it = mem_next.find(mem);
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if(it != std::end(mem_next))
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{
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++line_num;
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@ -785,10 +825,11 @@ struct BtorDumper
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str = stringf("%d array %d %d", line_num, memory->width, address_bits);
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d eq 1 %d %d", line_num, mem, line_num - 1);
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str = stringf("%d eq 1 %d %d; mem invar", line_num, mem, line_num - 1);
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f << stringf("%s\n", str.c_str());
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mem = line_num - 1;
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}
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}
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*/
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++line_num;
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if(polarity)
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str = stringf("%d one 1", line_num);
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@ -804,14 +845,15 @@ struct BtorDumper
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++line_num;
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str = stringf("%d write %d %d %d %d %d", line_num, data_width, address_width, mem, address, data);
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f << stringf("%s\n", str.c_str());
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/*
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++line_num;
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str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2/*enable*/, line_num-1, mem);
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str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2, line_num-1, mem);
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1);
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f << stringf("%s\n", str.c_str());
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mem_next.insert(mem);
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line_ref[cell->name]=line_num;
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*/
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mem_next[mem].insert(std::make_pair(line_num-1, line_num));
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}
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else if(cell->type == "$slice")
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{
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@ -975,6 +1017,12 @@ struct BtorDumper
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dump_cell(cell_it->second);
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}
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log("writing memory next");
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for(auto mem_it = module->memories.begin(); mem_it != module->memories.end(); ++mem_it)
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{
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dump_memory_next(mem_it->second);
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}
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for(auto it: safety)
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dump_property(it);
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@ -1,18 +0,0 @@
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proc;
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opt; opt_const -mux_undef; opt;
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rename -hide;;;
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#converting pmux to mux
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techmap -share_map pmux2mux.v;;
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#explicit type conversion
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splice; opt;
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#extracting memories;
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memory_dff -wr_only; memory_collect;;
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#flatten design
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flatten;;
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#converting asyn memory write to syn memory
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memory_unpack;
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#cell output to be a single wire
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splitnets -driver;
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setundef -zero -undriven;
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opt;;;
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@ -0,0 +1,435 @@
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% IEEEtran howto:
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% http://ftp.univie.ac.at/packages/tex/macros/latex/contrib/IEEEtran/IEEEtran_HOWTO.pdf
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\documentclass[9pt,technote,a4paper]{IEEEtran}
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\usepackage[T1]{fontenc} % required for luximono!
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\usepackage[scaled=0.8]{luximono} % typewriter font with bold face
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% To install the luximono font files:
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% getnonfreefonts-sys --all or
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% getnonfreefonts-sys luximono
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%
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% when there are trouble you might need to:
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% - Create /etc/texmf/updmap.d/99local-luximono.cfg
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% containing the single line: Map ul9.map
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% - Run update-updmap followed by mktexlsr and updmap-sys
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%
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% This commands must be executed as root with a root environment
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% (i.e. run "sudo su" and then execute the commands in the root
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% shell, don't just prefix the commands with "sudo").
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\usepackage[unicode,bookmarks=false]{hyperref}
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\usepackage[english]{babel}
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\usepackage[utf8]{inputenc}
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\usepackage{amssymb}
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\usepackage{amsmath}
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\usepackage{amsfonts}
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\usepackage{units}
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\usepackage{nicefrac}
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\usepackage{eurosym}
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\usepackage{graphicx}
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\usepackage{verbatim}
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\usepackage{algpseudocode}
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\usepackage{scalefnt}
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\usepackage{xspace}
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\usepackage{color}
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\usepackage{colortbl}
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\usepackage{multirow}
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\usepackage{hhline}
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\usepackage{listings}
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\usepackage{float}
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\usepackage{tikz}
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\usetikzlibrary{calc}
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\usetikzlibrary{arrows}
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\usetikzlibrary{scopes}
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\usetikzlibrary{through}
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\usetikzlibrary{shapes.geometric}
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\lstset{basicstyle=\ttfamily,frame=trBL,xleftmargin=2em,xrightmargin=1em,numbers=left}
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\begin{document}
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\title{Yosys Application Note 012: \\ Converting Verilog to BTOR}
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\author{Ahmed Irfan and Clifford Wolf \\ November 2014}
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\maketitle
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\begin{abstract}
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Verilog-2005 is a powerful Hardware Description Language (HDL) that
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can be used to easily create complex designs from small HDL code.
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BTOR~\cite{btor} is a bit-precise word-level format for model
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checking. It is simple format and easy to parse. It allows to model
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the model checking problem over theory of bit-vectors with
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one-dimensional arrays, thus enabling to model verilog designs with
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registers and memories. Yosys \cite{yosys} is an Open-Source Verilog
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synthesis tool that can be used to convert Verilog designs with simple
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assertions to BTOR format.
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\end{abstract}
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\section{Installation}
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Yosys written in C++ (using features from C++11) and is tested on
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modern Linux. It should compile fine on most UNIX systems with a
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C++11 compiler. The README file contains useful information on
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building Yosys and its prerequisites.
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Yosys is a large and feature-rich program with some dependencies. For
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this work, we may deactivate other extra features that are {\tt TCL},
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{\tt Qt}, {\tt MiniSAT}, and {\tt yosys-abc} support in the {\tt
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Makefile}.
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\bigskip
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This Application Note is based on GIT Rev. {\tt d3c67ad} from
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2014-09-22 of Yosys \cite{yosys}.
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%The Verilog sources used for the examples are taken from
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%yosys-bigsim \cite{bigsim}, a collection of real-world designs used for
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%regression testing Yosys.
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\section{Quick Start}
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We assume that the Verilog design is synthesizable and we also assume
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that the design does not have multi-dimensional memories. As BTOR
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implicitly initializes registers to zero value and memories stay
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uninitilized, we assume that the the Verilog design does
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not contain initial block. For more details about the BTOR format,
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please refer to~\cite{btor}.
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We provide a shell script {\tt verilog2btor.sh} which can be used to
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convert a Verilog design to BTOR. The script can be found in {\tt
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backends/btor} directory. Following example shows its usage:
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\begin{figure}[H]
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\begin{lstlisting}[language=sh]
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verilog2btor.sh fsm.v fsm.btor test
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\end{lstlisting}
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\renewcommand{\figurename}{Listing}
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\caption{Using verilog2btor script}
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\end{figure}
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The script {\tt verilog2btor.sh} takes three parameters. In the above
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example, first parameter {\tt fsm.v} is the input design, second
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parameter {\tt fsm.btor} is the file name of BTOR output, and third
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parameter {\tt test} is the name of top module in the design.
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To specify the properties (that need to be checked), we have two
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options:
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\begin{itemize}
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\item We can use simple {\tt assert} command in the procedural block
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or continuous block of the Verilog design, as shown in
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Listing~\ref{specifying_property_assert}. This is preferred option.
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\item We can use a output wire (single bit), whose name starts with
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{\tt safety}. The value of this output wire needs to be handled in
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the Verilog code, as shown in
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Listing~\ref{specifying_property_output}.
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\end{itemize}
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\begin{figure}[H]
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\begin{lstlisting}[language=Verilog]
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module test(input clk, input rst, output y);
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reg [2:0] state;
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output safety1;
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always @(posedge clk) begin
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if (rst || state == 3) begin
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state <= 0;
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end else begin
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assert(state < 3);
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state <= state + 1;
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end
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end
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assign y = state[2];
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assert property (y !== 1'b1);
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endmodule
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\end{lstlisting}
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\renewcommand{\figurename}{Listing}
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\caption{Specifying property in Verilog design with {\tt assert}}
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\label{specifying_property_assert}
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\end{figure}
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\begin{figure}[H]
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\begin{lstlisting}[language=Verilog]
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module test(input clk, input rst, output y,
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output safety1);
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reg [2:0] state;
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output safety1;
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always @(posedge clk) begin
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if (rst || state == 3)
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state <= 0;
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else
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state <= state + 1;
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end
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assign y = state[2];
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always @(*)
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begin
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if (y !== 1'b1)
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safety1 <= 1;
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else
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safety1 <= 0;
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end
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endmodule
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\end{lstlisting}
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\renewcommand{\figurename}{Listing}
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\caption{Specifying property in Verilog design with output wire}
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\label{specifying_property_output}
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\end{figure}
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We can run Boolector~$1.4$~\cite{boolector} on the generated BTOR
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file. The url for boolector provided in the references, contains
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installation and usage guide.
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We can also run nuXmv~\cite{nuxmv} but on the BTOR designs that does
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not have memories. With the next release of nuXmv, we will be also
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able to verify the designs with memories.
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\section{Detailed Flow}
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Yosys is able to synthesize the Verilog designs up to the gate level.
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We are interested in keeping registers and memories when synthesizing
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the design. For this purpose, we describe a customized Yosys synthesis
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flow, that is also provided as a script {\tt verilog2btor.sh} in Yosys
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distribution. The following script shows the operations that are
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performed in {\tt verilog2btor.sh}:
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\begin{figure}[H]
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\begin{lstlisting}[language=sh]
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read_verilog -sv $1;
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hierarchy -top $3; hierarchy -libdir $DIR;
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hierarchy -check;
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proc; opt;
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opt_const -mux_undef; opt;
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rename -hide;;;
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splice; opt;
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memory_dff -wr_only; memory_collect;;
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flatten;;
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memory_unpack;
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splitnets -driver;
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setundef -zero -undriven;
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opt;;;
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write_btor $2;
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\end{lstlisting}
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\renewcommand{\figurename}{Listing}
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\caption{Synthesis Flow for BTOR with memories}
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\label{btor_script_memory}
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\end{figure}
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Here is short description of what is happening in the script line by
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line:
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\begin{enumerate}
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\item Reading the input file.
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\item Setting the top module in the hierarchy and trying to read
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automatically the files which are given as {\tt include} in the file
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read in first line.
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\item Checking the design heirarchy.
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\item Converting processes to multiplexers (muxs) and flip-flops.
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\item Removing undef signals from muxs.
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\item Hiding the signals that are not used.
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\item Explicit type conversion, by introducing slice and concat cells
|
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in the circuit.
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\item Converting write memories to synchronuos memories, and
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collecting the memories to multiport memories.
|
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\item Flattening the design to get only one module.
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\item Separating read and write memories.
|
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\item Splitting the signals that are partially assigned
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\item Setting undef to zero value.
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\item Final optimization pass.
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\item Writing BTOR file.
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\end{enumerate}
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|
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For detailed description of the commands mentioned above, please refer
|
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to documentation of Yosys~\cite{yosys}.
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||||
|
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The script presented earlier can be easily modified to have a BTOR
|
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file that does not contain memories. This is done by removing the line
|
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number~8 and 10, and introduces a new command {\tt memory} at line
|
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number~8. Following is the modified yosys script file:
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|
||||
\begin{figure}[H]
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\begin{lstlisting}[language=sh]
|
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read_verilog -sv $1;
|
||||
hierarchy -top $3; hierarchy -libdir $DIR;
|
||||
hierarchy -check;
|
||||
proc; opt;
|
||||
opt_const -mux_undef; opt;
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||||
rename -hide;;;
|
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splice; opt;
|
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memory;;
|
||||
flatten;;
|
||||
splitnets -driver;
|
||||
setundef -zero -undriven;
|
||||
opt;;;
|
||||
write_btor $2;
|
||||
\end{lstlisting}
|
||||
\renewcommand{\figurename}{Listing}
|
||||
\caption{Synthesis Flow for BTOR without memories}
|
||||
\label{btor_script_without_memory}
|
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\end{figure}
|
||||
|
||||
\section{Example}
|
||||
|
||||
Here is an example verilog design that we want to convert to BTOR:
|
||||
|
||||
\begin{figure}[H]
|
||||
\begin{lstlisting}[language=Verilog]
|
||||
module array(input clk);
|
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reg [7:0] counter;
|
||||
reg [7:0] mem [7:0];
|
||||
always @(posedge clk) begin
|
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counter <= counter + 8'd1;
|
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mem[counter] <= counter;
|
||||
end
|
||||
assert property (!(counter > 8'd0) ||
|
||||
mem[counter - 8'd1] == counter - 8'd1);
|
||||
endmodule
|
||||
\end{lstlisting}
|
||||
\renewcommand{\figurename}{Listing}
|
||||
\caption{Example - Verilog Design}
|
||||
\label{example_verilog}
|
||||
\end{figure}
|
||||
|
||||
The generated BTOR file that contain memories, using the script shown
|
||||
in Listing~\ref{btor_script_memory}:
|
||||
\begin{figure}[H]
|
||||
\begin{lstlisting}[numbers=none]
|
||||
1 var 1 clk
|
||||
2 array 8 3
|
||||
3 var 8 $auto$rename.cc:150:execute$20
|
||||
4 const 8 00000001
|
||||
5 sub 8 3 4
|
||||
6 slice 3 5 2 0
|
||||
7 read 8 2 6
|
||||
8 slice 3 3 2 0
|
||||
9 add 8 3 4
|
||||
10 const 8 00000000
|
||||
11 ugt 1 3 10
|
||||
12 not 1 11
|
||||
13 const 8 11111111
|
||||
14 slice 1 13 0 0
|
||||
15 one 1
|
||||
16 eq 1 1 15
|
||||
17 and 1 16 14
|
||||
18 write 8 3 2 8 3
|
||||
19 acond 8 3 17 18 2
|
||||
20 anext 8 3 2 19
|
||||
21 eq 1 7 5
|
||||
22 or 1 12 21
|
||||
23 const 1 1
|
||||
24 one 1
|
||||
25 eq 1 23 24
|
||||
26 cond 1 25 22 24
|
||||
27 root 1 -26
|
||||
28 cond 8 1 9 3
|
||||
29 next 8 3 28
|
||||
\end{lstlisting}
|
||||
\renewcommand{\figurename}{Listing}
|
||||
\caption{Example - Converted BTOR with memory}
|
||||
\label{example_btor}
|
||||
\end{figure}
|
||||
|
||||
Here is the BTOR file obtained by the script shown in
|
||||
Listing~\ref{btor_script_without_memory} which expands the memory
|
||||
into individual elements:
|
||||
\begin{figure}[H]
|
||||
\begin{lstlisting}[numbers=none]
|
||||
1 var 1 clk
|
||||
2 var 8 mem[0]
|
||||
3 var 8 $auto$rename.cc:150:execute$20
|
||||
4 slice 3 3 2 0
|
||||
5 slice 1 4 0 0
|
||||
6 not 1 5
|
||||
7 slice 1 4 1 1
|
||||
8 not 1 7
|
||||
9 slice 1 4 2 2
|
||||
10 not 1 9
|
||||
11 and 1 8 10
|
||||
12 and 1 6 11
|
||||
13 cond 8 12 3 2
|
||||
14 cond 8 1 13 2
|
||||
15 next 8 2 14
|
||||
16 const 8 00000001
|
||||
17 add 8 3 16
|
||||
18 const 8 00000000
|
||||
19 ugt 1 3 18
|
||||
20 not 1 19
|
||||
21 var 8 mem[2]
|
||||
22 and 1 7 10
|
||||
23 and 1 6 22
|
||||
24 cond 8 23 3 21
|
||||
25 cond 8 1 24 21
|
||||
26 next 8 21 25
|
||||
27 sub 8 3 16
|
||||
.
|
||||
.
|
||||
.
|
||||
54 cond 1 53 50 52
|
||||
55 root 1 -54
|
||||
.
|
||||
.
|
||||
.
|
||||
77 cond 8 76 3 44
|
||||
78 cond 8 1 77 44
|
||||
79 next 8 44 78
|
||||
\end{lstlisting}
|
||||
\renewcommand{\figurename}{Listing}
|
||||
\caption{Example - Converted BTOR without memory}
|
||||
\label{example_btor}
|
||||
\end{figure}
|
||||
|
||||
\section{Limitations}
|
||||
|
||||
BTOR does not support initialization of memories and registers are
|
||||
implicitly initialized to value zero, so the initial block for
|
||||
memories need to be removed when converting to BTOR. This should be
|
||||
also kept in consideration that BTOR does not handle multi-dimensional
|
||||
memories, and does not support {\tt x} or {\tt z} value of Verilog.
|
||||
|
||||
|
||||
\section{Conclusion}
|
||||
|
||||
Using the described flow, we can use Yosys to generate word-level
|
||||
verification benchmarks with or without memories from Verilog design.
|
||||
|
||||
\begin{thebibliography}{9}
|
||||
|
||||
\bibitem{yosys}
|
||||
Clifford Wolf. The Yosys Open SYnthesis Suite. \\
|
||||
\url{http://www.clifford.at/yosys/}
|
||||
|
||||
%\bibitem{bigsim}
|
||||
%yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\
|
||||
%\url{https://github.com/cliffordwolf/yosys-bigsim}
|
||||
|
||||
%\bibitem{navre}
|
||||
%Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\
|
||||
%\url{http://opencores.org/project,navre}
|
||||
|
||||
%\bibitem{amber}
|
||||
%Conor Santifort. Amber ARM-compatible core. \\
|
||||
%\url{http://opencores.org/project,amber}
|
||||
|
||||
%\bibitem{ABC}
|
||||
%Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. \\
|
||||
%\url{http://www.eecs.berkeley.edu/~alanmi/abc/}
|
||||
|
||||
\bibitem{boolector}
|
||||
Robert Brummayer and Armin Biere, Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays\\
|
||||
\url{http://fmv.jku.at/boolector/}
|
||||
|
||||
\bibitem{btor}
|
||||
Robert Brummayer and Armin Biere and Florian Lonsing, BTOR:
|
||||
Bit-Precise Modelling of Word-Level Problems for Model Checking\\
|
||||
\url{http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf}
|
||||
|
||||
\bibitem{nuxmv}
|
||||
Roberto Cavada and Alessandro Cimatti and Michele Dorigatti and
|
||||
Alberto Griggio and Alessandro Mariotti and Andrea Micheli and Sergio
|
||||
Mover and Marco Roveri and Stefano Tonetta, The nuXmv Symbolic Model
|
||||
Checker\\
|
||||
\url{https://es-static.fbk.eu/tools/nuxmv/index.php}
|
||||
|
||||
\end{thebibliography}
|
||||
|
||||
|
||||
\end{document}
|
||||
Loading…
Reference in New Issue