Clifford Wolf
|
089c1e176f
|
Bugfix in handling of multi-dimensional memories
|
2015-09-23 07:56:17 +02:00 |
Clifford Wolf
|
559929e341
|
Warning for $display/$write outside initial block
|
2015-09-23 07:16:03 +02:00 |
Clifford Wolf
|
6176f4d081
|
Fixed multi-level prefix resolving
|
2015-09-22 20:52:02 +02:00 |
Andrew Zonenberg
|
c469f22144
|
Improvements to $display system task
|
2015-09-19 10:33:37 +02:00 |
Clifford Wolf
|
9db05d17fe
|
Added AST_INITIAL checks for $finish and $display
|
2015-09-18 09:50:57 +02:00 |
Andrew Zonenberg
|
7141f65533
|
Initial implementation of $display()
|
2015-09-18 09:36:46 +02:00 |
Andrew Zonenberg
|
e446e651cb
|
Initial implementation of $finish()
|
2015-09-18 09:30:25 +02:00 |
Clifford Wolf
|
eb38722e98
|
Fixed handling of memory read without address
|
2015-08-22 14:46:42 +02:00 |
Larry Doolittle
|
022f570563
|
Keep gcc from complaining about uninitialized variables
|
2015-08-14 23:26:49 +02:00 |
Clifford Wolf
|
84bf862f7c
|
Spell check (by Larry Doolittle)
|
2015-08-14 10:56:05 +02:00 |
Clifford Wolf
|
8d6d5c30d9
|
Added WORDS parameter to $meminit
|
2015-07-31 10:40:09 +02:00 |
Clifford Wolf
|
4513ff1b85
|
Fixed nested mem2reg
|
2015-07-29 16:37:08 +02:00 |
Clifford Wolf
|
6c84341f22
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
Clifford Wolf
|
13983e8318
|
Fixed handling of parameters with reversed range
|
2015-06-08 14:03:06 +02:00 |
Clifford Wolf
|
99b8746d27
|
Fixed signedness of genvar expressions
|
2015-05-29 20:08:00 +02:00 |
Clifford Wolf
|
1f1deda888
|
Added non-std verilog assume() statement
|
2015-02-26 18:47:39 +01:00 |
Clifford Wolf
|
d5ce9a32ef
|
Added deep recursion warning to AST simplify
|
2015-02-20 10:33:20 +01:00 |
Clifford Wolf
|
dc1a0f06fc
|
Parser support for complex delay expressions
|
2015-02-20 10:21:36 +01:00 |
Clifford Wolf
|
e9368a1d7e
|
Various fixes for memories with offsets
|
2015-02-14 14:21:15 +01:00 |
Clifford Wolf
|
7f1a1759d7
|
Added "read_verilog -nomeminit" and "nomeminit" attribute
|
2015-02-14 11:21:12 +01:00 |
Clifford Wolf
|
a8e9d37c14
|
Creating $meminit cells in verilog front-end
|
2015-02-14 10:49:30 +01:00 |
Clifford Wolf
|
cd919abdf1
|
Added AstNode::simplify() recursion counter
|
2015-02-13 12:33:12 +01:00 |
Clifford Wolf
|
2a9ad48eb6
|
Added ENABLE_NDEBUG makefile options
|
2015-01-24 12:16:46 +01:00 |
Clifford Wolf
|
df9d096a7d
|
Ignoring more system task and functions
|
2015-01-15 13:08:19 +01:00 |
Clifford Wolf
|
a588a4a5c9
|
Fixed handling of "input foo; reg [0:0] foo;"
|
2015-01-15 12:53:12 +01:00 |
Clifford Wolf
|
8e8e791fb5
|
Consolidate "Blocking assignment to memory.." msgs for the same line
|
2015-01-15 12:41:52 +01:00 |
Clifford Wolf
|
90bc71dd90
|
dict/pool changes in ast
|
2014-12-29 03:11:50 +01:00 |
Clifford Wolf
|
12ca6538a4
|
Fixed mem2reg warning message
|
2014-12-27 03:26:30 +01:00 |
Clifford Wolf
|
fe829bdbdc
|
Added log_warning() API
|
2014-11-09 10:44:23 +01:00 |
Clifford Wolf
|
37aa2e02db
|
AST simplifier: optimize constant AST_CASE nodes before recursively descending
|
2014-10-29 08:29:51 +01:00 |
Clifford Wolf
|
c4a2b3c1e9
|
Improvements in $readmem[bh] implementation
|
2014-10-26 23:29:36 +01:00 |
Clifford Wolf
|
70b2efdb05
|
Added support for $readmemh/$readmemb
|
2014-10-26 20:33:10 +01:00 |
Clifford Wolf
|
84ffe04075
|
Fixed various VS warnings
|
2014-10-18 15:20:38 +02:00 |
William Speirs
|
fda52f05f2
|
Wrapped math in int constructor
|
2014-10-17 11:28:14 +02:00 |
Clifford Wolf
|
6b05a9e807
|
Fixed handling of invalid array access in mem2reg code
|
2014-10-16 00:44:23 +02:00 |
Clifford Wolf
|
4569a747f8
|
Renamed SIZE() to GetSize() because of name collision on Win32
|
2014-10-10 17:07:24 +02:00 |
Clifford Wolf
|
48b00dccea
|
Another $clog2 bugfix
|
2014-09-08 12:25:23 +02:00 |
Clifford Wolf
|
680eaaac41
|
Fixed $clog2 (off by one error)
|
2014-09-06 19:31:04 +02:00 |
Ruben Undheim
|
79cbf9067c
|
Corrected spelling mistakes found by lintian
|
2014-09-06 08:47:06 +02:00 |
Clifford Wolf
|
ad146c2582
|
Fixed small memory leak in ast simplify
|
2014-08-21 17:33:40 +02:00 |
Clifford Wolf
|
6c5cafcd8b
|
Added support for DPI function with different names in C and Verilog
|
2014-08-21 17:22:04 +02:00 |
Clifford Wolf
|
490d7a5bf2
|
Fixed memory leak in DPI function calls
|
2014-08-21 13:09:47 +02:00 |
Clifford Wolf
|
7bfc4ae120
|
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
|
2014-08-21 12:43:51 +02:00 |
Clifford Wolf
|
640d9fc551
|
Added "via_celltype" attribute on task/func
|
2014-08-18 14:29:30 +02:00 |
Clifford Wolf
|
acb435b6cf
|
Added const folding of AST_CASE to AST simplifier
|
2014-08-18 00:02:30 +02:00 |
Clifford Wolf
|
85e3cc12ac
|
Fixed handling of task outputs
|
2014-08-14 22:26:10 +02:00 |
Clifford Wolf
|
d259abbda2
|
Added AST_MULTIRANGE (arrays with more than 1 dimension)
|
2014-08-06 15:52:54 +02:00 |
Clifford Wolf
|
91dd87e60b
|
Improved scope resolution of local regs in Verilog+AST frontend
|
2014-08-05 12:15:53 +02:00 |
Clifford Wolf
|
0129d41efa
|
Fixed AST handling of variables declared inside a functions main block
|
2014-08-05 08:35:51 +02:00 |
Clifford Wolf
|
768eb846c4
|
More bugfixes related to new RTLIL::IdString
|
2014-08-02 18:14:21 +02:00 |
Clifford Wolf
|
14412e6c95
|
Preparations for RTLIL::IdString redesign: cleanup of existing code
|
2014-08-02 00:45:25 +02:00 |
Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
48822e79a3
|
Removed left over debug code
|
2014-07-28 19:38:30 +02:00 |
Clifford Wolf
|
ec58965967
|
Fixed part selects of parameters
|
2014-07-28 19:24:28 +02:00 |
Clifford Wolf
|
27a872d1e7
|
Added support for "upto" wires to Verilog front- and back-end
|
2014-07-28 14:25:03 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
309d64d46a
|
Fixed two memory leaks in ast simplify
|
2014-07-25 13:24:10 +02:00 |
Clifford Wolf
|
20a7965f61
|
Various small fixes (from gcc compiler warnings)
|
2014-07-23 20:45:27 +02:00 |
Clifford Wolf
|
9b183539af
|
Implemented dynamic bit-/part-select for memory writes
|
2014-07-17 16:49:23 +02:00 |
Clifford Wolf
|
5867f6bcdc
|
Added support for bit/part select to mem2reg rewriter
|
2014-07-17 13:49:32 +02:00 |
Clifford Wolf
|
6d69d4aaa8
|
Added support for constant bit- or part-select for memory writes
|
2014-07-17 13:13:21 +02:00 |
Clifford Wolf
|
543551b80a
|
changes in verilog frontend for new $mem/$memwr WR_EN interface
|
2014-07-16 12:49:50 +02:00 |
Clifford Wolf
|
55a1b8dbac
|
Fixed processing of initial values for block-local variables
|
2014-07-11 13:05:53 +02:00 |
Clifford Wolf
|
076182c34e
|
Fixed handling of mixed real/int ternary expressions
|
2014-06-25 10:05:36 +02:00 |
Clifford Wolf
|
80e4594695
|
Added AstNode::MEM2REG_FL_CMPLX_LHS
|
2014-06-17 21:39:25 +02:00 |
Clifford Wolf
|
798ff88855
|
Improved handling of relational op of real values
|
2014-06-17 12:47:51 +02:00 |
Clifford Wolf
|
6c17d4f242
|
Improved ternary support for real values
|
2014-06-16 15:12:24 +02:00 |
Clifford Wolf
|
82bbd2f077
|
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
|
2014-06-16 15:05:37 +02:00 |
Clifford Wolf
|
48dc6ab98d
|
Improved AstNode::asReal for large integers
|
2014-06-15 08:38:31 +02:00 |
Clifford Wolf
|
149fe83a8d
|
improved (fixed) conversion of real values to bit vectors
|
2014-06-14 21:00:51 +02:00 |
Clifford Wolf
|
d5765b5e14
|
Fixed relational operators for const real expressions
|
2014-06-14 19:33:58 +02:00 |
Clifford Wolf
|
f3b4a9dd24
|
Added support for math functions
|
2014-06-14 13:36:23 +02:00 |
Clifford Wolf
|
9bd7d5c468
|
Added handling of real-valued parameters/localparams
|
2014-06-14 12:00:47 +02:00 |
Clifford Wolf
|
fc7b6d172a
|
Implemented more real arithmetic
|
2014-06-14 11:27:05 +02:00 |
Clifford Wolf
|
442a8e2875
|
Implemented basic real arithmetic
|
2014-06-14 08:51:22 +02:00 |
Clifford Wolf
|
e275e8eef9
|
Add support for cell arrays
|
2014-06-07 11:48:50 +02:00 |
Clifford Wolf
|
0b1ce63a19
|
Added support for repeat stmt in const functions
|
2014-06-07 10:47:53 +02:00 |
Clifford Wolf
|
7c8a7b2131
|
further improved const function support
|
2014-06-07 00:02:05 +02:00 |
Clifford Wolf
|
76da2fe172
|
improved const function support
|
2014-06-06 22:55:02 +02:00 |
Clifford Wolf
|
5c10d2ee36
|
fix functions with no block (but single statement, loop, etc.)
|
2014-06-06 21:29:23 +02:00 |
Clifford Wolf
|
ab54ce17c8
|
improved ast simplify of const functions
|
2014-06-06 17:40:45 +02:00 |
Clifford Wolf
|
d6a01fe412
|
Fixed merging of compatible wire decls in AST frontend
|
2014-03-05 19:55:58 +01:00 |
Clifford Wolf
|
de7bd12004
|
Bugfix in recursive AST simplification
|
2014-03-05 19:45:33 +01:00 |
Clifford Wolf
|
f8c9143b2b
|
Fixed bug in generation of undefs for $memwr MUXes
|
2014-02-22 17:08:00 +01:00 |
Clifford Wolf
|
7ac524e8e8
|
Improved support for constant functions
|
2014-02-16 13:16:38 +01:00 |
Clifford Wolf
|
45d2b6ffce
|
Be more conservative with new const-function code
|
2014-02-14 20:45:30 +01:00 |
Clifford Wolf
|
e8af3def7f
|
Added support for FOR loops in function calls in parameters
|
2014-02-14 20:33:22 +01:00 |
Clifford Wolf
|
534c1a5dd0
|
Created basic support for function calls in parameter values
|
2014-02-14 19:56:44 +01:00 |
Clifford Wolf
|
f4f230d7cc
|
Fixed gcc compiler warnings with release build
|
2014-02-06 22:49:14 +01:00 |
Clifford Wolf
|
d267bcde4e
|
Fixed bug in sequential sat proofs and improved handling of asserts
|
2014-02-04 12:46:16 +01:00 |
Clifford Wolf
|
d06258f74f
|
Added constant size expression support of sized constants
|
2014-02-01 13:50:23 +01:00 |
Clifford Wolf
|
4df7e03ec9
|
Bugfix in name resolution with generate blocks
|
2014-01-30 15:01:28 +01:00 |
Clifford Wolf
|
88fbdd4916
|
Fixed algorithmic complexity of AST simplification of long expressions
|
2014-01-20 20:25:20 +01:00 |
Clifford Wolf
|
1e67099b77
|
Added $assert cell
|
2014-01-19 14:03:40 +01:00 |
Clifford Wolf
|
a3d94bf888
|
Fixed typo in frontends/ast/simplify.cc
|
2014-01-12 21:04:42 +01:00 |
Clifford Wolf
|
364f277afb
|
Fixed a stupid access after delete bug
|
2013-12-29 20:18:22 +01:00 |
Clifford Wolf
|
ecc30255ba
|
Added proper === and !== support in constant expressions
|
2013-12-27 13:50:08 +01:00 |
Clifford Wolf
|
891e4b5b0d
|
Keep strings as strings in const ternary and concat
|
2013-12-05 13:26:17 +01:00 |
Clifford Wolf
|
e935bb6eda
|
Added const folding support for $signed and $unsigned
|
2013-12-05 13:09:41 +01:00 |
Clifford Wolf
|
853538d78b
|
Fixed generate-for (and disabled double warning for auto-wire)
|
2013-12-04 21:33:00 +01:00 |
Clifford Wolf
|
3c220e0b32
|
Added support for $clog2 system function
|
2013-12-04 21:19:54 +01:00 |
Clifford Wolf
|
4a4a3fc337
|
Various improvements in support for generate statements
|
2013-12-04 21:06:54 +01:00 |
Clifford Wolf
|
507c63d112
|
Added support for local regs in named blocks
|
2013-12-04 09:10:16 +01:00 |
Clifford Wolf
|
019b301541
|
Early wire/reg/parameter width calculation in ast/simplify
|
2013-11-24 19:40:23 +01:00 |
Clifford Wolf
|
95c94a02fc
|
Fixed async proc detection in mem2reg
|
2013-11-21 21:26:56 +01:00 |
Clifford Wolf
|
09471846c5
|
Major improvements in mem2reg and added "init" sync rules
|
2013-11-21 13:49:00 +01:00 |
Clifford Wolf
|
65ad556f3d
|
Another name resolution bugfix for generate blocks
|
2013-11-20 13:57:40 +01:00 |
Clifford Wolf
|
c4c299eb5a
|
Do not allow memory bit select on the left side of an assignment
|
2013-11-20 12:18:46 +01:00 |
Clifford Wolf
|
ac2be2d892
|
Fixed name resolution of local tasks and functions in generate block
|
2013-11-20 11:05:58 +01:00 |
Clifford Wolf
|
19dba2561e
|
Implemented part/bit select on memory read
|
2013-11-20 10:51:32 +01:00 |
Clifford Wolf
|
4f2edcf2f9
|
Fixed two bugs in mem2reg functionality in AST frontend
|
2013-11-18 19:55:12 +01:00 |
Clifford Wolf
|
de03184150
|
Fixed mem2reg for reg usage outside always block
|
2013-11-18 12:35:41 +01:00 |
Clifford Wolf
|
9f49d538e1
|
Fixed handling of different signedness in power operands
|
2013-11-08 11:06:11 +01:00 |
Clifford Wolf
|
4abc8e695a
|
Implemented const folding of ternary op with undef select
|
2013-11-08 04:44:09 +01:00 |
Clifford Wolf
|
fc6dc0d7b8
|
Fixed handling of power operator
|
2013-11-07 22:20:00 +01:00 |
Clifford Wolf
|
d7cb62ac96
|
Fixed more extend vs. extend_u0 issues
|
2013-11-07 19:20:20 +01:00 |
Clifford Wolf
|
02f4f89fdb
|
Disabled const folding of ternary op when select is undef
|
2013-11-07 18:18:16 +01:00 |
Clifford Wolf
|
ed4bcd52e5
|
Fixed sign handling in constants
|
2013-11-07 14:53:10 +01:00 |
Clifford Wolf
|
83a8b8b5ca
|
Fixed const folding in corner cases with parameters
|
2013-11-07 14:08:53 +01:00 |
Clifford Wolf
|
536621a98b
|
Fixed at_zero evaluation of dynamic ranges
|
2013-11-07 11:25:19 +01:00 |
Clifford Wolf
|
f050c40519
|
Various fixes for correct parameter support
|
2013-11-07 10:02:11 +01:00 |
Clifford Wolf
|
f2786df146
|
Another fix for early width and sign detection in ast simplifier
|
2013-11-04 21:29:36 +01:00 |
Clifford Wolf
|
d38c67f53d
|
Fixed const folding of ternary operator
|
2013-11-04 16:46:14 +01:00 |
Clifford Wolf
|
8d226da694
|
Use proper bit width ans sign extension for const folding
|
2013-11-04 15:37:09 +01:00 |
Clifford Wolf
|
1325514d33
|
Fixes for early width and sign detection in ast simplifier
|
2013-11-04 08:28:13 +01:00 |
Clifford Wolf
|
472117d532
|
further improved early width and sign detection in ast simplifier
|
2013-11-04 06:04:42 +01:00 |
Clifford Wolf
|
ada80545fa
|
Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
|
2013-11-02 21:13:01 +01:00 |
Clifford Wolf
|
943329c1dc
|
Various ast changes for early expression width detection (prep for constfold fixes)
|
2013-11-02 13:00:17 +01:00 |
Clifford Wolf
|
23cf23418c
|
Fixed handling of boolean attributes (frontends)
|
2013-10-24 11:20:13 +02:00 |
Johann Glaser
|
6c4cbc03c2
|
Added support for notif0/notif1 primitives
|
2013-08-20 11:23:59 +02:00 |
Clifford Wolf
|
8656b1c08f
|
Added support for bufif0/bufif1 primitives
|
2013-08-19 19:50:04 +02:00 |
Clifford Wolf
|
4214561890
|
Improved ast dumping (ast/verilog frontend)
|
2013-08-19 19:49:14 +02:00 |
Clifford Wolf
|
56432a920f
|
Added defparam support to Verilog/AST frontend
|
2013-07-04 14:12:33 +02:00 |
Clifford Wolf
|
59dd02baa2
|
Fixes and improvements in AST const folding
|
2013-06-10 13:56:03 +02:00 |
Clifford Wolf
|
db98a18edb
|
Enabled AST/Verilog front-end optimizations per default
|
2013-06-10 13:19:04 +02:00 |
Clifford Wolf
|
c5ee2b306a
|
Merge branch 'bugfix'
|
2013-05-16 16:44:45 +02:00 |
Clifford Wolf
|
6cc8e848b6
|
Fixed synthesis of functions in latched blocks
|
2013-05-16 16:44:06 +02:00 |
Clifford Wolf
|
161565be10
|
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
|
2013-03-31 11:19:11 +02:00 |
Clifford Wolf
|
7a99349de4
|
Improvements and bugfixes for generate blocks with local signals
|
2013-03-26 11:31:34 +01:00 |
Clifford Wolf
|
6a382f2aba
|
Fixed handling of unconditional generate blocks
|
2013-03-26 09:44:54 +01:00 |
Clifford Wolf
|
227520f94d
|
Added nosync attribute and some async reset related fixes
|
2013-03-25 17:13:14 +01:00 |
Clifford Wolf
|
df9753d398
|
Added mem2reg option to verilog frontend
|
2013-03-24 11:13:32 +01:00 |
Clifford Wolf
|
3a5244e913
|
Another fix in mem2reg ast simplify logic
|
2013-03-24 10:42:08 +01:00 |
Clifford Wolf
|
bb3357c027
|
Improved mem2reg handling in ast simplifier
|
2013-03-24 09:27:01 +01:00 |
Clifford Wolf
|
e45d1c8865
|
Tiny fixes to verilog parser
|
2013-03-23 18:54:31 +01:00 |
Clifford Wolf
|
a321a5c412
|
Moved stand-alone libs to libs/ directory and added libs/subcircuit
|
2013-02-27 09:32:19 +01:00 |
Clifford Wolf
|
4f0c2862a0
|
Added support for verilog genblock[index].member syntax
|
2013-02-26 13:18:22 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |