Clifford Wolf
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14412e6c95
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Preparations for RTLIL::IdString redesign: cleanup of existing code
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2014-08-02 00:45:25 +02:00 |
Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
Clifford Wolf
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48822e79a3
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Removed left over debug code
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2014-07-28 19:38:30 +02:00 |
Clifford Wolf
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ec58965967
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Fixed part selects of parameters
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2014-07-28 19:24:28 +02:00 |
Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
Clifford Wolf
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309d64d46a
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Fixed two memory leaks in ast simplify
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2014-07-25 13:24:10 +02:00 |
Clifford Wolf
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20a7965f61
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Various small fixes (from gcc compiler warnings)
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2014-07-23 20:45:27 +02:00 |
Clifford Wolf
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9b183539af
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Implemented dynamic bit-/part-select for memory writes
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2014-07-17 16:49:23 +02:00 |
Clifford Wolf
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5867f6bcdc
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Added support for bit/part select to mem2reg rewriter
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2014-07-17 13:49:32 +02:00 |
Clifford Wolf
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6d69d4aaa8
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Added support for constant bit- or part-select for memory writes
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2014-07-17 13:13:21 +02:00 |
Clifford Wolf
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543551b80a
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changes in verilog frontend for new $mem/$memwr WR_EN interface
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2014-07-16 12:49:50 +02:00 |
Clifford Wolf
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55a1b8dbac
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Fixed processing of initial values for block-local variables
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2014-07-11 13:05:53 +02:00 |
Clifford Wolf
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076182c34e
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Fixed handling of mixed real/int ternary expressions
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2014-06-25 10:05:36 +02:00 |
Clifford Wolf
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80e4594695
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Added AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:39:25 +02:00 |
Clifford Wolf
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798ff88855
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Improved handling of relational op of real values
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2014-06-17 12:47:51 +02:00 |
Clifford Wolf
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6c17d4f242
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Improved ternary support for real values
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2014-06-16 15:12:24 +02:00 |
Clifford Wolf
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82bbd2f077
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Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
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2014-06-16 15:05:37 +02:00 |
Clifford Wolf
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48dc6ab98d
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Improved AstNode::asReal for large integers
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2014-06-15 08:38:31 +02:00 |
Clifford Wolf
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149fe83a8d
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improved (fixed) conversion of real values to bit vectors
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2014-06-14 21:00:51 +02:00 |
Clifford Wolf
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d5765b5e14
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Fixed relational operators for const real expressions
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2014-06-14 19:33:58 +02:00 |
Clifford Wolf
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f3b4a9dd24
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Added support for math functions
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2014-06-14 13:36:23 +02:00 |
Clifford Wolf
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9bd7d5c468
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Added handling of real-valued parameters/localparams
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2014-06-14 12:00:47 +02:00 |
Clifford Wolf
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fc7b6d172a
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Implemented more real arithmetic
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2014-06-14 11:27:05 +02:00 |
Clifford Wolf
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442a8e2875
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Implemented basic real arithmetic
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2014-06-14 08:51:22 +02:00 |
Clifford Wolf
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e275e8eef9
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Add support for cell arrays
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2014-06-07 11:48:50 +02:00 |
Clifford Wolf
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0b1ce63a19
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Added support for repeat stmt in const functions
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2014-06-07 10:47:53 +02:00 |
Clifford Wolf
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7c8a7b2131
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further improved const function support
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2014-06-07 00:02:05 +02:00 |
Clifford Wolf
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76da2fe172
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improved const function support
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2014-06-06 22:55:02 +02:00 |
Clifford Wolf
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5c10d2ee36
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fix functions with no block (but single statement, loop, etc.)
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2014-06-06 21:29:23 +02:00 |
Clifford Wolf
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ab54ce17c8
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improved ast simplify of const functions
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2014-06-06 17:40:45 +02:00 |
Clifford Wolf
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d6a01fe412
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Fixed merging of compatible wire decls in AST frontend
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2014-03-05 19:55:58 +01:00 |
Clifford Wolf
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de7bd12004
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Bugfix in recursive AST simplification
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2014-03-05 19:45:33 +01:00 |
Clifford Wolf
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f8c9143b2b
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Fixed bug in generation of undefs for $memwr MUXes
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2014-02-22 17:08:00 +01:00 |
Clifford Wolf
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7ac524e8e8
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Improved support for constant functions
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2014-02-16 13:16:38 +01:00 |
Clifford Wolf
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45d2b6ffce
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Be more conservative with new const-function code
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2014-02-14 20:45:30 +01:00 |
Clifford Wolf
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e8af3def7f
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Added support for FOR loops in function calls in parameters
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2014-02-14 20:33:22 +01:00 |
Clifford Wolf
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534c1a5dd0
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Created basic support for function calls in parameter values
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2014-02-14 19:56:44 +01:00 |
Clifford Wolf
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f4f230d7cc
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Fixed gcc compiler warnings with release build
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2014-02-06 22:49:14 +01:00 |
Clifford Wolf
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d267bcde4e
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Fixed bug in sequential sat proofs and improved handling of asserts
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2014-02-04 12:46:16 +01:00 |
Clifford Wolf
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d06258f74f
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Added constant size expression support of sized constants
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2014-02-01 13:50:23 +01:00 |
Clifford Wolf
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4df7e03ec9
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Bugfix in name resolution with generate blocks
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2014-01-30 15:01:28 +01:00 |
Clifford Wolf
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88fbdd4916
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Fixed algorithmic complexity of AST simplification of long expressions
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2014-01-20 20:25:20 +01:00 |
Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |
Clifford Wolf
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a3d94bf888
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Fixed typo in frontends/ast/simplify.cc
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2014-01-12 21:04:42 +01:00 |
Clifford Wolf
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364f277afb
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Fixed a stupid access after delete bug
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2013-12-29 20:18:22 +01:00 |
Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
Clifford Wolf
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891e4b5b0d
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Keep strings as strings in const ternary and concat
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2013-12-05 13:26:17 +01:00 |
Clifford Wolf
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e935bb6eda
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Added const folding support for $signed and $unsigned
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2013-12-05 13:09:41 +01:00 |
Clifford Wolf
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853538d78b
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Fixed generate-for (and disabled double warning for auto-wire)
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2013-12-04 21:33:00 +01:00 |
Clifford Wolf
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3c220e0b32
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Added support for $clog2 system function
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2013-12-04 21:19:54 +01:00 |
Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
Clifford Wolf
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507c63d112
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Added support for local regs in named blocks
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2013-12-04 09:10:16 +01:00 |
Clifford Wolf
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019b301541
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Early wire/reg/parameter width calculation in ast/simplify
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2013-11-24 19:40:23 +01:00 |
Clifford Wolf
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95c94a02fc
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Fixed async proc detection in mem2reg
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2013-11-21 21:26:56 +01:00 |
Clifford Wolf
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09471846c5
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Major improvements in mem2reg and added "init" sync rules
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2013-11-21 13:49:00 +01:00 |
Clifford Wolf
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65ad556f3d
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Another name resolution bugfix for generate blocks
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2013-11-20 13:57:40 +01:00 |
Clifford Wolf
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c4c299eb5a
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Do not allow memory bit select on the left side of an assignment
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2013-11-20 12:18:46 +01:00 |
Clifford Wolf
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ac2be2d892
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Fixed name resolution of local tasks and functions in generate block
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2013-11-20 11:05:58 +01:00 |
Clifford Wolf
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19dba2561e
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Implemented part/bit select on memory read
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2013-11-20 10:51:32 +01:00 |
Clifford Wolf
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4f2edcf2f9
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Fixed two bugs in mem2reg functionality in AST frontend
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2013-11-18 19:55:12 +01:00 |
Clifford Wolf
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de03184150
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Fixed mem2reg for reg usage outside always block
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2013-11-18 12:35:41 +01:00 |
Clifford Wolf
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9f49d538e1
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Fixed handling of different signedness in power operands
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2013-11-08 11:06:11 +01:00 |
Clifford Wolf
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4abc8e695a
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Implemented const folding of ternary op with undef select
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2013-11-08 04:44:09 +01:00 |
Clifford Wolf
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fc6dc0d7b8
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
Clifford Wolf
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d7cb62ac96
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Fixed more extend vs. extend_u0 issues
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2013-11-07 19:20:20 +01:00 |
Clifford Wolf
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02f4f89fdb
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Disabled const folding of ternary op when select is undef
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2013-11-07 18:18:16 +01:00 |
Clifford Wolf
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ed4bcd52e5
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Fixed sign handling in constants
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2013-11-07 14:53:10 +01:00 |
Clifford Wolf
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83a8b8b5ca
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Fixed const folding in corner cases with parameters
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2013-11-07 14:08:53 +01:00 |
Clifford Wolf
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536621a98b
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Fixed at_zero evaluation of dynamic ranges
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2013-11-07 11:25:19 +01:00 |
Clifford Wolf
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f050c40519
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Various fixes for correct parameter support
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2013-11-07 10:02:11 +01:00 |
Clifford Wolf
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f2786df146
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Another fix for early width and sign detection in ast simplifier
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2013-11-04 21:29:36 +01:00 |
Clifford Wolf
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d38c67f53d
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Fixed const folding of ternary operator
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2013-11-04 16:46:14 +01:00 |
Clifford Wolf
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8d226da694
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Use proper bit width ans sign extension for const folding
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2013-11-04 15:37:09 +01:00 |
Clifford Wolf
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1325514d33
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Fixes for early width and sign detection in ast simplifier
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2013-11-04 08:28:13 +01:00 |
Clifford Wolf
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472117d532
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further improved early width and sign detection in ast simplifier
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2013-11-04 06:04:42 +01:00 |
Clifford Wolf
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ada80545fa
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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
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2013-11-02 21:13:01 +01:00 |
Clifford Wolf
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943329c1dc
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Various ast changes for early expression width detection (prep for constfold fixes)
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2013-11-02 13:00:17 +01:00 |
Clifford Wolf
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23cf23418c
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Fixed handling of boolean attributes (frontends)
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2013-10-24 11:20:13 +02:00 |
Johann Glaser
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6c4cbc03c2
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Added support for notif0/notif1 primitives
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2013-08-20 11:23:59 +02:00 |
Clifford Wolf
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8656b1c08f
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Added support for bufif0/bufif1 primitives
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2013-08-19 19:50:04 +02:00 |
Clifford Wolf
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4214561890
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Improved ast dumping (ast/verilog frontend)
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2013-08-19 19:49:14 +02:00 |
Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
Clifford Wolf
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59dd02baa2
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Fixes and improvements in AST const folding
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2013-06-10 13:56:03 +02:00 |
Clifford Wolf
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db98a18edb
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Enabled AST/Verilog front-end optimizations per default
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2013-06-10 13:19:04 +02:00 |
Clifford Wolf
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c5ee2b306a
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Merge branch 'bugfix'
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2013-05-16 16:44:45 +02:00 |
Clifford Wolf
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6cc8e848b6
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Fixed synthesis of functions in latched blocks
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2013-05-16 16:44:06 +02:00 |
Clifford Wolf
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161565be10
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
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2013-03-31 11:19:11 +02:00 |
Clifford Wolf
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7a99349de4
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Improvements and bugfixes for generate blocks with local signals
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2013-03-26 11:31:34 +01:00 |
Clifford Wolf
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6a382f2aba
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Fixed handling of unconditional generate blocks
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2013-03-26 09:44:54 +01:00 |
Clifford Wolf
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227520f94d
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Added nosync attribute and some async reset related fixes
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2013-03-25 17:13:14 +01:00 |
Clifford Wolf
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df9753d398
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Added mem2reg option to verilog frontend
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2013-03-24 11:13:32 +01:00 |
Clifford Wolf
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3a5244e913
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Another fix in mem2reg ast simplify logic
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2013-03-24 10:42:08 +01:00 |
Clifford Wolf
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bb3357c027
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Improved mem2reg handling in ast simplifier
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2013-03-24 09:27:01 +01:00 |
Clifford Wolf
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e45d1c8865
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Tiny fixes to verilog parser
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2013-03-23 18:54:31 +01:00 |
Clifford Wolf
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a321a5c412
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
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2013-02-27 09:32:19 +01:00 |
Clifford Wolf
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4f0c2862a0
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Added support for verilog genblock[index].member syntax
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2013-02-26 13:18:22 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |