Eddie Hung
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e273ed5275
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Wrap SRL{16,32} too
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2019-08-20 15:09:38 -07:00 |
Eddie Hung
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808f07630f
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Wrap LUTRAMs in order to capture comb/seq behaviour
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2019-08-20 14:49:11 -07:00 |
Eddie Hung
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c00d72cdb3
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Minor refactor
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2019-08-20 14:47:58 -07:00 |
Eddie Hung
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0079e9b4a6
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Add LUTRAM delays
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2019-08-20 13:53:38 -07:00 |
Eddie Hung
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505d062daf
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Fix use of {CLK,EN}_POLARITY, also add a FIXME
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2019-08-20 13:33:31 -07:00 |
Eddie Hung
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8d0cffaf20
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Remove mapping rules
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2019-08-20 13:11:39 -07:00 |
Eddie Hung
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33960dd3d8
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Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
[WIP] synth xilinx renaming, as per #1184
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2019-08-20 12:55:26 -07:00 |
Eddie Hung
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5eda5fc7eb
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Remove -icells
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2019-08-20 12:41:11 -07:00 |
Eddie Hung
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be9e4f1b67
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Use abc_{map,unmap,model}.v
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2019-08-20 12:39:11 -07:00 |
Eddie Hung
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c4d4c6db3f
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-20 12:00:12 -07:00 |
Eddie Hung
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14c03861b6
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Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
Refactor abc9 to use port attributes, not module attributes
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2019-08-20 11:59:31 -07:00 |
Eddie Hung
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d9fe4cccbf
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
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2019-08-20 11:57:52 -07:00 |
SergeyDegtyar
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71dd412ac5
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Fix tests; Remove simulation;
- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
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2019-08-20 15:52:25 +03:00 |
Clifford Wolf
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ba71e4f8f2
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Merge pull request #1298 from YosysHQ/clifford/pmgen
Improvements in pmgen
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2019-08-20 11:39:42 +02:00 |
Clifford Wolf
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d0117d7d12
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Merge branch 'master' into clifford/pmgen
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2019-08-20 11:39:23 +02:00 |
Clifford Wolf
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6ffb910d12
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Add test case for real parameters
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-20 11:38:21 +02:00 |
Clifford Wolf
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c25c1e742b
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Merge pull request #1308 from jakobwenzel/real_params
Handle real values when deriving ast modules
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2019-08-20 11:37:26 +02:00 |
SergeyDegtyar
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153ec0541c
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Add new tests for ice40 architecture
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2019-08-20 07:50:05 +03:00 |
whitequark
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749ff864aa
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Merge pull request #1309 from whitequark/proc_clean-fix-1268
proc_clean: fix order of switch insertion
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2019-08-20 00:45:41 +00:00 |
Eddie Hung
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1f03154a0c
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-19 15:19:32 -07:00 |
Eddie Hung
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526e081342
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Add arrival times for SRL outputs
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2019-08-19 15:15:43 -07:00 |
Eddie Hung
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45d4b33f0c
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Output i/o/h extensions even if no boxes or flops
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2019-08-19 13:17:31 -07:00 |
Eddie Hung
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b71212ddea
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Add BRAM arrival times
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2019-08-19 12:46:35 -07:00 |
Eddie Hung
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e29df7d5fa
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Remove debug
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2019-08-19 12:44:43 -07:00 |
Eddie Hung
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2f86366087
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Add reference to source of Tclktoq timing
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2019-08-19 12:39:22 -07:00 |
Eddie Hung
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91687d3fea
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Add (* abc_arrival *) attribute
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2019-08-19 12:33:24 -07:00 |
Eddie Hung
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d02ef8c73f
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Add 'abc_arrival' attribute for flop outputs
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2019-08-19 11:32:18 -07:00 |
Eddie Hung
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f25837f8e8
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Update box timings
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2019-08-19 11:31:40 -07:00 |
Eddie Hung
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ba2261e21a
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Move from cell attr to module attr
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2019-08-19 11:18:33 -07:00 |
Eddie Hung
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3f4886e7a3
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Fix typo
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2019-08-19 10:42:00 -07:00 |
Eddie Hung
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7e010834eb
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Fix typo
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2019-08-19 10:41:18 -07:00 |
Eddie Hung
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f42ba811b6
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ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
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2019-08-19 10:11:47 -07:00 |
Eddie Hung
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2f4e0a5388
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-19 10:07:27 -07:00 |
Eddie Hung
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29e4c8bd06
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Clarify with 'only'
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2019-08-19 10:00:53 -07:00 |
Eddie Hung
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c36fca86f7
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Update doc
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2019-08-19 09:59:57 -07:00 |
Eddie Hung
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d81a090d89
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Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
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2019-08-19 09:56:17 -07:00 |
Eddie Hung
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e301440a0b
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Use attributes instead of params
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2019-08-19 09:51:49 -07:00 |
whitequark
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4a942ba7b9
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proc_clean: fix order of switch insertion.
Fixes #1268.
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2019-08-19 16:44:23 +00:00 |
Eddie Hung
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9bfe924e17
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Set abc_flop and use it in toposort
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2019-08-19 09:40:01 -07:00 |
Eddie Hung
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10c69f71e9
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Use %d
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2019-08-19 09:16:20 -07:00 |
Jakob Wenzel
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24971fda87
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handle real values when deriving ast modules
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2019-08-19 14:17:36 +02:00 |
Clifford Wolf
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4adcbecec5
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Merge pull request #1306 from mmicko/gitignore_fix
Ignore all generated headers for pmgen pass
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2019-08-19 13:09:12 +02:00 |
Clifford Wolf
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21699e5840
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Add *.sv to tests/simple_abc9/.gitignore
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-19 13:04:57 +02:00 |
Clifford Wolf
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1e3dd0a2da
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
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2019-08-19 13:04:06 +02:00 |
Clifford Wolf
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3edb0abed8
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Merge pull request #1305 from YosysHQ/clifford/testfast
Speed up "make test" and related cleanups
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2019-08-19 12:58:09 +02:00 |
Eddie Hung
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e34f2de55d
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Merge remote-tracking branch 'origin/master' into clifford/testfast
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2019-08-18 21:29:15 -07:00 |
Eddie Hung
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f5170a7eda
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Removal of more `stat` calls from tests
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2019-08-18 21:28:45 -07:00 |
Miodrag Milanovic
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4a32e29445
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Merge remote-tracking branch 'upstream/master' into anlogic_fixes
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2019-08-18 11:47:46 +02:00 |
Miodrag Milanovic
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dbe3cb9708
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Ignore all generated headers for pmgen pass
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2019-08-18 10:49:17 +02:00 |
whitequark
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98a54353b7
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Merge pull request #1290 from YosysHQ/eddie/pr1266_again
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER (retry)
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2019-08-18 08:04:26 +00:00 |