riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Clarify with 'only'

This commit is contained in:
Eddie Hung 2019-08-19 10:00:53 -07:00
parent c36fca86f7
commit 29e4c8bd06
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -420,7 +420,7 @@ Verilog Attributes and non-standard features
- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
carry-out (if output port) ports of a box. This information is necessary for
`abc9` to preserve the integrity of carry-chains. Specifying this attribute
onto a bus port will affect its most significant bit.
onto a bus port will affect only its most significant bit.
Non-standard or SystemVerilog features for formal verification