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@ -417,9 +417,10 @@ Verilog Attributes and non-standard features
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port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
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as a combinatorial loop.
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- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark
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the carry-in and carry-out ports of a box. This information is necessary for
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`abc9` to preserve the integrity of carry-chains.
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- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
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carry-out (if output port) ports of a box. This information is necessary for
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`abc9` to preserve the integrity of carry-chains. Specifying this attribute
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onto a bus port will affect its most significant bit.
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Non-standard or SystemVerilog features for formal verification
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