mirror of https://github.com/YosysHQ/yosys.git
handle real values when deriving ast modules
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@ -1502,7 +1502,10 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
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rewrite_parameter:
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para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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delete child->children.at(0);
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if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0)
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if ((parameters[para_id].flags & RTLIL::CONST_FLAG_REAL) != 0) {
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child->children[0] = new AstNode(AST_REALVALUE);
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child->children[0]->realvalue = std::stod(parameters[para_id].decode_string());
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} else if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0)
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child->children[0] = AstNode::mkconst_str(parameters[para_id].decode_string());
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else
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child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0);
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