Johann Glaser
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667543de0b
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improved help for "select"
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2014-02-05 15:53:02 +01:00 |
Clifford Wolf
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3b5c462273
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presentation progress
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2014-02-05 15:06:13 +01:00 |
Clifford Wolf
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9f6364c1c4
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presentation progress
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2014-02-05 13:12:50 +01:00 |
Clifford Wolf
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aa8e754ae5
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Added read_verilog -setattr
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2014-02-05 11:22:10 +01:00 |
Clifford Wolf
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5bf33de24a
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Added setattr and setparam commands
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2014-02-05 11:11:55 +01:00 |
Clifford Wolf
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078cecf9ea
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Updated todo items in README file
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2014-02-05 01:59:30 +01:00 |
Clifford Wolf
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aa9da46807
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Removed old unused files from tests/
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2014-02-05 01:55:39 +01:00 |
Clifford Wolf
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968ae31cac
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Added support for dump -append
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2014-02-04 23:45:30 +01:00 |
Clifford Wolf
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1fb8ba73bd
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Throw errors if non-existing selection variables are used
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2014-02-04 23:31:06 +01:00 |
Clifford Wolf
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b1bf55dd63
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Added select -none
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2014-02-04 23:23:44 +01:00 |
Clifford Wolf
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e0c867db53
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presentation progress
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2014-02-04 23:00:48 +01:00 |
Clifford Wolf
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99b9c56da1
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Fixed detection of init attribute in opt_rmdff
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2014-02-04 23:00:32 +01:00 |
Clifford Wolf
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69e867f3e8
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Added support for inline commands to abc -script
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2014-02-04 22:01:53 +01:00 |
Clifford Wolf
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03d63dd861
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presentation progress
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2014-02-04 16:51:12 +01:00 |
Clifford Wolf
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7a5f378bae
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Added hierarchy -purge_lib option
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2014-02-04 16:50:13 +01:00 |
Clifford Wolf
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7a66b38c3e
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Added test cases for sat command
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2014-02-04 13:43:34 +01:00 |
Clifford Wolf
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6891fd79a3
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added sat -falsify
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2014-02-04 13:34:37 +01:00 |
Clifford Wolf
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d267bcde4e
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Fixed bug in sequential sat proofs and improved handling of asserts
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2014-02-04 12:46:16 +01:00 |
Clifford Wolf
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ecdf1f5577
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Improved handling of reg init in opt_share and opt_rmdff
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2014-02-04 12:02:47 +01:00 |
Clifford Wolf
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9e938aa32a
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presentation progress
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2014-02-04 00:57:11 +01:00 |
Clifford Wolf
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6c3d767976
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presentation progress
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2014-02-03 16:26:27 +01:00 |
Clifford Wolf
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9e35021585
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Addred sat option -ignore_unknown_cells
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2014-02-03 16:26:10 +01:00 |
Clifford Wolf
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a6750b3753
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
Clifford Wolf
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de9226a64f
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Replaced isim with xsim in tests/tools/autotest.sh, removed xst support
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2014-02-03 13:00:55 +01:00 |
Clifford Wolf
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de336d93b2
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More opt_const -mux_bool features
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2014-02-02 22:41:24 +01:00 |
Clifford Wolf
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982c9da011
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presentation progress
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2014-02-02 22:26:26 +01:00 |
Clifford Wolf
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9d0b69edaa
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Added opt_const -mux_bool
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2014-02-02 22:11:08 +01:00 |
Clifford Wolf
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bee4450c4c
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Added support for inverter chains to opt_const
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2014-02-02 21:46:42 +01:00 |
Clifford Wolf
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f9c4d33909
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Added RTLIL::SigSpec::to_single_sigbit()
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2014-02-02 21:35:26 +01:00 |
Clifford Wolf
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67b0ce2578
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Only generate write-enable $and if WE is not constant 1 in memory_map
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2014-02-02 21:27:26 +01:00 |
Clifford Wolf
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83fa652820
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Added constant-clock case to opt_rmdff
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2014-02-02 21:09:08 +01:00 |
Clifford Wolf
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6983d3f10b
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presentation progress
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2014-02-02 17:57:14 +01:00 |
Clifford Wolf
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aa732b0c73
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Added show -notitle option
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2014-02-02 17:55:32 +01:00 |
Clifford Wolf
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9808acdc75
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Added delete command
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2014-02-02 17:11:19 +01:00 |
Clifford Wolf
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a9e2d86f86
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Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax
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2014-02-02 16:47:17 +01:00 |
Clifford Wolf
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0f88e28693
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presentation progress
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2014-02-02 13:30:49 +01:00 |
Clifford Wolf
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9334c34170
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presentation progress
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2014-02-02 13:06:28 +01:00 |
Clifford Wolf
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cdd6e11af5
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Added support for blanks after -I and -D in read_verilog
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2014-02-02 13:06:21 +01:00 |
Clifford Wolf
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f4f0bd6eef
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Fixed a bug in miter command
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2014-02-01 22:53:27 +01:00 |
Clifford Wolf
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374674aff4
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Added sat -show-inputs and -show-outputs
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2014-02-01 22:52:44 +01:00 |
Clifford Wolf
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caf540d1ad
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Added show -color support for cells and finished show -label implementation
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2014-02-01 18:23:32 +01:00 |
Clifford Wolf
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af325bf206
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Fixed comment/eol parsing in ilang frontend
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2014-02-01 17:28:02 +01:00 |
Clifford Wolf
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d06258f74f
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Added constant size expression support of sized constants
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2014-02-01 13:50:23 +01:00 |
Clifford Wolf
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1e2440e7ed
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Added note about SystemVerilog assert statement to README
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2014-02-01 13:04:49 +01:00 |
Clifford Wolf
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fa92722358
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Added miter command
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2014-02-01 10:35:56 +01:00 |
Clifford Wolf
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1c8f6f21b4
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Progress on presentation
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2014-01-31 12:48:31 +01:00 |
Clifford Wolf
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ed8ad99960
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More changes to techlibs/common/simlib.v for LEC
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2014-01-31 11:21:29 +01:00 |
Clifford Wolf
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36a808c572
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presentation progress
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2014-01-30 15:25:09 +01:00 |
Clifford Wolf
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4df7e03ec9
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Bugfix in name resolution with generate blocks
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2014-01-30 15:01:28 +01:00 |
Clifford Wolf
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672229eda5
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Added yosys -H for command list
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2014-01-30 12:32:59 +01:00 |