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Added note about SystemVerilog assert statement to README
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README
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README
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@ -270,6 +270,11 @@ Verilog Attributes and non-standard features
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for everything that comes after the {* ... *} statement. (Reset
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by adding an empty {* *} statement.)
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- The "assert" statement from SystemVerilog is supported in its most basic
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form. In module context: "assert property (<expression>);" and within an
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always block: "assert(<expression>);". It is transformed to a $assert cell
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that is supported by the "sat" and "write_btor" commands.
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Workarounds for known build problems
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====================================
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