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Updated todo items in README file

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Clifford Wolf 2014-02-05 01:59:30 +01:00
parent aa9da46807
commit 078cecf9ea
1 changed files with 2 additions and 2 deletions
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@ -308,8 +308,7 @@ Roadmap / Large-scale TODOs
- Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
- Implement SAT-based formal equivialence checker
- Rewrite freduce pass with input-cone analysis
- Write equiv pass, base hypothesis on input cones
- Write equiv pass based on hint-based register mapping
- Re-implement Verilog frontend (far future)
- cleaner (easier to use, harder to use wrong) AST format
@ -323,6 +322,7 @@ Other Unsorted TODOs
- Implement missing Verilog 2005 features:
- Multi-dimensional arrays
- Support for real (float) const. expressions and parameters
- ROM modeling using $readmemh/$readmemb in "initial" blocks
- Ignore what needs to be ignored (e.g. drive and charge strengths)
- Check standard vs. implementation to identify missing features