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yosys
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340 Commits

Author SHA1 Message Date
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Andrew Zonenberg 52a738a544 Added GP_DAC cell 2016-07-11 22:45:55 -07:00
Andrew Zonenberg baae472b83 Removed VOUT port of GP_BANDGAP 2016-07-11 22:45:42 -07:00
Andrew Zonenberg 8619d33114 Removed splitnets in prep for new gp4par parser 2016-07-11 22:42:25 -07:00
Clifford Wolf cdb58f68ab Added "prep -auto-top" and "synth -auto-top" 2016-07-11 11:40:55 +02:00
whitequark c0645839fe greenpak4: add GP_COUNT{8,14}_ADV cells. 2016-07-10 15:46:46 +00:00
Clifford Wolf 21659847a7 Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
Clifford Wolf df5ebfa0a0 Improved ice40_ffinit error reporting 2016-06-30 09:58:13 +02:00
Clifford Wolf ca91bccb6b Added "deminout" 2016-06-19 13:08:16 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf 99edf24966 Added "nlutmap -assert" 2016-06-09 11:47:41 +02:00
Clifford Wolf 52b0b4e31e Do not run "wreduce" in "prep -ifx" 2016-06-08 12:14:32 +02:00
Clifford Wolf 2032e6d8e4 Added "proc_mux -ifx" 2016-06-06 17:15:50 +02:00
Andrew Zonenberg 47eace0b9f Added GP_DELAY cell 2016-05-07 21:29:26 -07:00
Andrew Zonenberg 41bbad4e4c Fixed typo in port name 2016-05-07 21:14:42 -07:00
Andrew Zonenberg b5171541cd Fixed extra semicolon 2016-05-07 21:14:18 -07:00
Andrew Zonenberg 85ee88b0ee Fixed typo in parameter name 2016-05-07 21:14:00 -07:00
Andrew Zonenberg a0c19aae55 Added simulation timescale declaration 2016-05-07 21:13:47 -07:00
Clifford Wolf 6fe3d5a1cf Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Clifford Wolf 126da0ad3d Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" 2016-05-06 14:32:32 +02:00
Andrew Zonenberg 2096a05ec2 Changed order of passes for better handling of INIT attributes on "output reg" FFs 2016-05-04 17:13:54 -07:00
Andrew Zonenberg dee1c27a19 Renamed module parameter 2016-05-04 17:03:45 -07:00
Andrew Zonenberg a613f171ae Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract 2016-05-04 15:55:16 -07:00
Andrew Zonenberg deb1eccab5 Fixed incorrect signal naming in GP_IOBUF 2016-05-04 08:06:18 -07:00
Andrew Zonenberg dcee3256d5 Added tri-state I/O extraction for GreenPak 2016-05-03 22:53:29 -07:00
Andrew Zonenberg 66095153fd Added GreenPak I/O buffer cells 2016-05-03 22:03:04 -07:00
Andrew Zonenberg 9fc9d5f1fb Added comment to clarify GP_ABUF cell 2016-05-02 20:29:39 -07:00
Andrew Zonenberg 79460208c9 Added GP_ABUF cell 2016-05-02 20:27:41 -07:00
Andrew Zonenberg 134e093e4e Added GP_PGA cell 2016-04-27 23:07:21 -07:00
Andrew Zonenberg d57c85111f Merge https://github.com/cliffordwolf/yosys 2016-04-24 22:11:56 -07:00
Andrew Zonenberg 349d717202 Removed VIN_BUF_EN 2016-04-24 17:01:21 -07:00
Andrew Zonenberg 6e215f374d Renamed VOUT to OUT on GP_ACMP cell 2016-04-23 22:53:49 -07:00
Andrew Zonenberg 512486dcf3 Added GP_ACMP cell 2016-04-23 22:33:36 -07:00
Clifford Wolf 09ffebb995 Added "prep -flatten" and "synth -flatten" 2016-04-24 00:48:33 +02:00
Clifford Wolf 77aa2031e7 Converted "prep" to ScriptPass 2016-04-24 00:48:06 +02:00
Clifford Wolf c9c5192cd6 Run clean after splitnets in synth_greenpak4 2016-04-23 23:09:45 +02:00
Clifford Wolf 34195f281f Merge https://github.com/azonenberg/yosys 2016-04-23 10:33:32 +02:00
Clifford Wolf f85cfa5666 Added "shregmap" to synth_greenpak4 2016-04-23 10:31:19 +02:00
Clifford Wolf a24021ea20 Converted synth_greenpak4 to ScriptPass 2016-04-23 10:27:33 +02:00
Andrew Zonenberg 0cbe70eaa4 Fixed typo 2016-04-22 19:08:19 -07:00
Andrew Zonenberg ab11f2aa70 Merge https://github.com/cliffordwolf/yosys 2016-04-22 19:07:55 -07:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Andrew Zonenberg d90c1e9522 Added GP_VREF cell 2016-04-20 20:48:19 -07:00
Andrew Zonenberg d0aaf8d262 Added GP_SHREG cell 2016-04-13 23:13:51 -07:00
Andrew Zonenberg cdefa60367 Refactoring: alphabetized cells_sim 2016-04-13 23:13:39 -07:00
Andrew Zonenberg f1679936fe Fixed missing semicolon 2016-04-09 01:18:02 -07:00