riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,475 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

3475 Commits

Author SHA1 Message Date
Clifford Wolf 92e4b5aa77 Add writeback mode to "sim" command 2017-08-17 15:54:51 +02:00
Clifford Wolf 7b4f3f86c3 Improve "sim" command 2017-08-17 12:27:08 +02:00
Clifford Wolf 864498527a Merge pull request #386 from azonenberg/gpak-counters 
Bug fixes to GP_COUNTx and GP_PGEN cells in GreenPAK technology library
 2017-08-16 15:58:29 +02:00
Clifford Wolf 75046aa531 Add "sim" command skeleton 2017-08-16 13:05:21 +02:00
Andrew Zonenberg e6eaf487b6 Fixed more issues with GreenPAK counter sim models 2017-08-15 09:18:36 -07:00
Andrew Zonenberg 3a404be62a Updated PGEN model to have level triggered reset (matches actual hardware behavior 2017-08-15 09:18:27 -07:00
Andrew Zonenberg e5109847c9 Fixed bug in GP_COUNTx model 2017-08-15 09:18:17 -07:00
Andrew Zonenberg 66b256d40e Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high 2017-08-15 09:18:07 -07:00
Clifford Wolf e9918365fd Merge branch 'azonenberg-rmports' 2017-08-15 11:32:55 +02:00
Clifford Wolf 88983f5012 Mostly coding style related fixes in rmports pass 2017-08-15 11:32:35 +02:00
Clifford Wolf 9fe6bc48a9 Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports 2017-08-15 11:19:55 +02:00
Clifford Wolf 2cf0b5c157 Merge pull request #381 from azonenberg/countfix 
Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
 2017-08-14 21:47:26 +02:00
Clifford Wolf 6d371f06ab Merge pull request #383 from azonenberg/abcfnames 
abc: Allow +/ filenames in the abc command
 2017-08-14 21:46:17 +02:00
Clifford Wolf 76efbcc15f Merge pull request #382 from azonenberg/jsoniofix 
json: Parse inout correctly rather than as an output
 2017-08-14 21:45:54 +02:00
Clifford Wolf 237b482b92 Merge pull request #384 from azonenberg/crtechlib 
CoolRunner-II technology library improvements
 2017-08-14 21:45:29 +02:00
Robert Ou 78fd24f40f coolrunner2: Add INVERT parameter to some BUFGs 2017-08-14 12:13:33 -07:00
Robert Ou 1e3ffd57cb coolrunner2: Add FFs with clock enable to cells_sim.v 2017-08-14 12:13:25 -07:00
Robert Ou 9a64ba3338 abc: Allow +/ filenames in the abc command 2017-08-14 12:11:11 -07:00
Robert Ou 366ce87cff json: Parse inout correctly rather than as an output 2017-08-14 12:09:03 -07:00
Andrew Zonenberg 15e41d6363 rmports: Now remove ports from cell instances if we optimized them out of that cell 2017-08-14 11:44:05 -07:00
Andrew Zonenberg 0ee27d0226 ProcessModule is no longer virtual (why was it in the first place?) 2017-08-14 11:18:09 -07:00
Andrew Zonenberg bd2ac68769 rmports now works on all modules in the design, not just the top. 2017-08-14 11:16:44 -07:00
Andrew Zonenberg d5e5bbad86 Updated Makefile to reflect opt_rmports being renamed to rmports 2017-08-14 11:04:56 -07:00
Andrew Zonenberg 1a6a23f91a Renamed opt_rmports pass to rmports 2017-08-14 11:00:45 -07:00
Andrew Zonenberg 348acbd968 Fixed typo in GP_COUNT8 sim model 2017-08-14 10:45:40 -07:00
Andrew Zonenberg c205d571df Fixed typo in error message 2017-08-14 10:45:40 -07:00
Andrew Zonenberg 0a6c702c41 Changed LEVEL resets for GP_COUNTx to be properly synthesizeable 2017-08-14 10:45:40 -07:00
Andrew Zonenberg 9f3dc59ffe Changed LEVEL resets to be edge triggered anyway 2017-08-14 10:45:40 -07:00
Andrew Zonenberg b049ead042 Added level-triggered reset support to GP_COUNTx simulation models 2017-08-14 10:45:40 -07:00
Andrew Zonenberg ac75524f69 Fixed undeclared "count" in GP_COUNT8_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg db20e3f1c2 Fixed undeclared "count" in GP_COUNT14_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 3618ca2218 Fixed typo in last commit 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4da1a327c0 Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else. 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4504dd78e9 Fixed typo in COUNT8 model 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 60dd5dba7b Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
Andrew Zonenberg f55d4cc2fd Improved cells_sim_digital model for GP_COUNT8 2017-08-14 10:45:39 -07:00
Andrew Zonenberg fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 1bb150c231 Improved handling of constant connections in opt_rmports 2017-08-14 10:28:19 -07:00
Andrew Zonenberg 2877d5e504 Fixed handling of cell ports that aren't wires 2017-08-14 10:28:16 -07:00
Andrew Zonenberg 3dd7f42e2b opt_rmports: Fixed incorrect handling of multi-bit nets 2017-08-14 10:28:11 -07:00
Andrew Zonenberg 66aac06eee Removed commented out debug code 2017-08-14 10:28:04 -07:00
Andrew Zonenberg cca3cb5fbb Added opt_rmports pass (remove unconnected ports from top-level modules) 2017-08-14 10:27:59 -07:00
Clifford Wolf 007f29b9c2 Add support for set-reset cell variants to opt_rmdff 2017-08-09 13:29:52 +02:00
Clifford Wolf 159701962a Auto-detect JSON front-end 2017-08-09 13:28:52 +02:00
Clifford Wolf c4a7958f70 Add handling of constant reset signals to opt_rmdff 2017-08-06 13:27:18 +02:00
Clifford Wolf 48b2b376d0 Add "yosys-smtbmc --smtc-init --smtc-top --noinit" 2017-08-04 17:09:08 +02:00
Clifford Wolf 1dc921d9a1 Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags" 2017-08-04 11:24:58 +02:00
Clifford Wolf 5c09f24e48 Fix typo in "abc" pass help message 2017-07-29 16:21:58 +02:00
Clifford Wolf 15073790bf Add merging of "past FFs" to verific importer 2017-07-29 00:10:38 +02:00
Clifford Wolf e7d1277a2c Add consolidation of init attributes to opt_clean, some opt_clean log fixes 2017-07-29 00:10:33 +02:00