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Merge pull request #384 from azonenberg/crtechlib 

CoolRunner-II technology library improvements
This commit is contained in:
Clifford Wolf 2017-08-14 21:45:29 +02:00 committed by GitHub
parent 007f29b9c2 78fd24f40f
commit 237b482b92
1 changed files with 66 additions and 2 deletions
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68
techlibs/coolrunner2/cells_sim.v
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@ -143,17 +143,21 @@ module BUFG(I, O);
endmodule
module BUFGSR(I, O);
parameter INVERT = 0;
input I;
output O;
assign O = I;
assign O = INVERT ? ~I : I;
endmodule
module BUFGTS(I, O);
parameter INVERT = 0;
input I;
output O;
assign O = I;
assign O = INVERT ? ~I : I;
endmodule
module FDDCP (C, PRE, CLR, D, Q);
@ -244,3 +248,63 @@ module FTDCP (C, PRE, CLR, T, Q);
assign Q = Q_;
endmodule
module FDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
module FDCPE_N (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
module FDDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule