riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2,710 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

2710 Commits

Author SHA1 Message Date
Clifford Wolf 375f83c5ec Fixed memory leak in ilang frontend 2013-05-23 12:55:59 +02:00
Clifford Wolf e04d88cf22 Added missing newline to some error messages 2013-05-23 11:19:33 +02:00
Clifford Wolf 6a38e767ba Added labels to "help -write-tex-command-reference-manual" output 2013-05-23 09:49:37 +02:00
Clifford Wolf ebb155b2d5 Added support for processes to show command 2013-05-23 09:15:51 +02:00
Clifford Wolf 04996657c8 Fixed show command for constant assignments 2013-05-23 08:22:44 +02:00
Clifford Wolf 3b8882ae49 Some improvements in opt_rmdff 2013-05-23 07:48:18 +02:00
Clifford Wolf 63e6a35ce2 Merge pull request #6 from hansiglaser/master 
added option '-Dname[=definition]' to command 'read_verilog'
 2013-05-19 16:07:55 -07:00
Johann Glaser 10a195c0a1 added option '-Dname[=definition]' to command 'read_verilog' 2013-05-19 17:07:52 +02:00
Clifford Wolf fbadb54b9b Removed test cases that have been moved to yosys-test. 
https://github.com/cliffordwolf/yosys-tests/
 2013-05-17 15:32:30 +02:00
Clifford Wolf 3ecc314238 Fixed to aggressive x-folding in opt_const 2013-05-17 14:55:18 +02:00
Clifford Wolf 59d0c75b98 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-05-16 16:51:47 +02:00
Clifford Wolf c5ee2b306a Merge branch 'bugfix' 2013-05-16 16:44:45 +02:00
Clifford Wolf 6cc8e848b6 Fixed synthesis of functions in latched blocks 2013-05-16 16:44:06 +02:00
Clifford Wolf ff4a1dd06c Improved vcdcd.pl (added -d option) 2013-05-14 09:41:47 +02:00
Clifford Wolf be8ecd6d16 Some improvements in vcdcd.pl 2013-05-14 08:50:59 +02:00
Clifford Wolf b56e06d2f5 Added support for verilog === operator 2013-05-07 14:35:40 +02:00
Clifford Wolf 595db0d7b9 Added tcl "yosys -import" command 2013-05-02 15:27:01 +02:00
Clifford Wolf 97f783e668 Improved/simplified TCL bindings 2013-05-01 14:21:03 +02:00
Clifford Wolf 83c743f717 Added support for const cell inputs in techmap 2013-04-27 18:30:29 +02:00
Clifford Wolf 7d0a274f12 Fixed README for new show command behavior (svg vs. ps) 2013-04-27 14:41:46 +02:00
Clifford Wolf b1cb4d7871 Added "flatten" pass 2013-04-26 14:40:45 +02:00
Clifford Wolf 8f2d90de4f Fixed handling of positional module parameters 2013-04-26 14:40:25 +02:00
Clifford Wolf 94744ac7b0 Fixed hierarchy pass for hierarchies of parametric modules 2013-04-26 13:28:15 +02:00
Clifford Wolf 453a29c9f6 Only use sha1 checksums for names of parametric modules when the verbose form is to long 2013-04-26 13:13:58 +02:00
Clifford Wolf e6dca3445a Fixed "show -format ..." command line parsing 2013-04-15 11:59:35 +02:00
Clifford Wolf 6626aad29a Added "submod -name ..." support 2013-04-15 11:58:24 +02:00
Clifford Wolf e0c408cb4a Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values 2013-04-13 21:19:10 +02:00
Clifford Wolf c6198ea5a8 Fixed a bug in opt_const when optimizing 1-bit compares with constants 2013-04-13 21:18:24 +02:00
Clifford Wolf db10275251 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-04-07 16:42:38 +02:00
Clifford Wolf 32dbf7752d Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v 2013-04-07 16:42:29 +02:00
Clifford Wolf 00a877e09b Merge pull request #5 from hansiglaser/master 
fsm_export: optionally use binary state encoding as state names instead of  s0, s1, ...
 2013-04-05 07:04:51 -07:00
Johann Glaser 7ef245aa7d fsm_export: optionally use binary state encoding as state names instead of 
s0, s1, ...
 2013-04-05 15:34:40 +02:00
Clifford Wolf ab74706338 Merge pull request #4 from hansiglaser/master 
fsm_export: specify KISS filename on command line
 2013-04-05 02:30:44 -07:00
Johann Glaser 9714072b28 fsm_export: specify KISS filename on command line 2013-04-05 11:17:49 +02:00
Clifford Wolf af4444e5b9 Fixed/improved handling of colored wires in show command 2013-04-01 14:58:43 +02:00
Clifford Wolf 32ee794bfb Added support for @<set-name> in expand select ops (%x, %ci, %co) 2013-04-01 14:58:11 +02:00
Clifford Wolf 5919bf5525 Removed 4096 bytes limit for size of command from script file 2013-04-01 14:38:05 +02:00
Clifford Wolf 3ec9fa4048 Added -color <color> <selection> option to show command 2013-04-01 14:12:17 +02:00
Clifford Wolf 9b1ce98db6 Fixed "select" for "%%" stmt with emty stack 2013-03-31 18:06:27 +02:00
Clifford Wolf b66e9fb348 Added "script" command 2013-03-31 18:05:31 +02:00
Clifford Wolf f1a2fd966f Now only use value from "initial" when no matching "always" block is found 2013-03-31 11:51:12 +02:00
Clifford Wolf 161565be10 Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) 2013-03-31 11:19:11 +02:00
Clifford Wolf 5640b7d607 Added test cases from 2012 paper on comparison of foss verilog synthesis tools 2013-03-31 11:17:56 +02:00
Clifford Wolf 04843bdcbe Added k68 (m68k compatible cpu) test case from verilator 2013-03-31 11:00:46 +02:00
Clifford Wolf 88af5b6a16 Improved opt_share for reduce cells 2013-03-29 11:19:21 +01:00
Clifford Wolf 0d48b846ac Improved opt_share for commutative standard cells 2013-03-29 11:01:26 +01:00
Clifford Wolf d60fbaf664 Added EXTRA_TARGETS Makefile variable 2013-03-28 16:53:40 +01:00
Clifford Wolf eff8c68dd9 Improved Makefile: Added ENABLE_* switches 2013-03-28 16:50:50 +01:00
Clifford Wolf 73fba5164f Implemented TCL support (only via -c option at the moment) 2013-03-28 12:26:17 +01:00
Clifford Wolf b9870a364e Improved subcircuit verbose output (added portmapper results) 2013-03-28 11:36:54 +01:00