Commit Graph

82 Commits

Author SHA1 Message Date
Eddie Hung 5939ffdc07 Forgot to slice 2019-08-23 13:06:59 -07:00
Eddie Hung 242b3083ea Cope with possibility that D could connect to Q on same cell 2019-08-23 13:06:31 -07:00
Eddie Hung 18b64609c2 xilinx_srl to use 'slice' features of pmgen for word level 2019-08-23 12:22:06 -07:00
Eddie Hung f4fd41d5d2 Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl 2019-08-23 11:35:06 -07:00
Clifford Wolf 55bf8f69e0 Fix port hanlding in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-23 16:26:54 +02:00
Clifford Wolf adb81ba386 Add pmgen slices and choices
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-23 16:15:50 +02:00
Eddie Hung 6e8fda8bf0 Add doc 2019-08-22 11:52:24 -07:00
Eddie Hung cabadb85e2 Add copyright 2019-08-22 11:25:19 -07:00
Eddie Hung 9f3ed1726e pmgen to also iterate over all module ports 2019-08-22 11:15:16 -07:00
Eddie Hung 74bd190d3b Remove output_bits 2019-08-22 11:14:59 -07:00
Eddie Hung 231ddbf95c Forgot to set ud_variable.minlen 2019-08-22 11:02:17 -07:00
Eddie Hung 61639d5387 Do not run xilinx_srl_pm in fixed loop 2019-08-22 10:51:04 -07:00
Eddie Hung d0b2973413 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:06 -07:00
Eddie Hung 7d02d17b16 Reuse var 2019-08-21 19:18:40 -07:00
Eddie Hung 5c8344363f Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b.
2019-08-21 19:18:27 -07:00
Eddie Hung 7e7965ca7b Trim shiftx_width when upper bits are 1'bx 2019-08-21 18:43:17 -07:00
Eddie Hung ed7be3e6b6 Add comment 2019-08-21 17:36:38 -07:00
Eddie Hung 15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung 6d76ae4c65 Rename pattern to fixed 2019-08-21 15:46:58 -07:00
Eddie Hung b0a3b430bf attribute -> attr 2019-08-21 15:44:07 -07:00
Eddie Hung 61b4d7ae13 Use Cell::has_keep_attribute() 2019-08-21 15:41:46 -07:00
Eddie Hung 6fa9e03e4c xilinx_srl to support FDRE and FDRE_1 2019-08-21 15:35:29 -07:00
Eddie Hung 3c8e8521a6 Fix polarity of EN_POL 2019-08-21 14:42:11 -07:00
Eddie Hung a980f0d4be Add CLKPOL == 0 2019-08-21 14:35:40 -07:00
Eddie Hung 1c7d721558 Reject if not minlen from inside pattern matcher 2019-08-21 14:26:24 -07:00
Eddie Hung cab2bd083e Get wire via SigBit 2019-08-21 13:47:47 -07:00
Eddie Hung 52fea5b658 Respect \keep on cells or wires 2019-08-21 13:42:03 -07:00
Eddie Hung 5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung df53fe12e7 Fix spacing 2019-08-21 12:54:11 -07:00
Eddie Hung 0250712486 Initial progress on xilinx_srl 2019-08-21 12:50:49 -07:00
Miodrag Milanovic 948b6f91a1 Fix test_pmgen deps 2019-08-21 17:00:24 +02:00
Eddie Hung 9b9d759451 Fix copy-paste typo 2019-08-20 20:18:51 -07:00
Clifford Wolf d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00
Clifford Wolf 1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00
Miodrag Milanovic dbe3cb9708 Ignore all generated headers for pmgen pass 2019-08-18 10:49:17 +02:00
Clifford Wolf f3405fb048 Refactor pmgen rollback mechanism
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 13:54:18 +02:00
Clifford Wolf 318ae0351c Improvements in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 13:53:55 +02:00
Clifford Wolf f95853c822 Add pmgen "fallthrough" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 11:29:37 +02:00
Eddie Hung cd5a372cd1 Add help() call 2019-08-16 13:00:12 -07:00
Clifford Wolf 64bd414e54 Minor bugfix in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 14:35:13 +02:00
Clifford Wolf 20910fd7c8 Add pmgen finish statement, return number of matches
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 14:16:35 +02:00
Clifford Wolf f45dad8220 Redesign pmgen backtracking for recursive matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 13:47:50 +02:00
Clifford Wolf c710df181c Add pmgen "generate" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 13:26:36 +02:00
Clifford Wolf 4a57b7e1ab Refactor demo_reduce into test_pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 11:47:51 +02:00
Clifford Wolf 016036f247 Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 23:02:37 +02:00
Clifford Wolf 969ab9027a Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 22:48:13 +02:00
Clifford Wolf eb80d3d43f Change pmgen default rule to reject, switch peepopt behavior to accept
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 22:47:59 +02:00
Clifford Wolf 03f98d9176 Add demo_reduce pass to demonstrace recursive pattern matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 18:36:39 +02:00
Clifford Wolf 73bf453929 Improvements in pmgen for recursive patterns
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 18:35:56 +02:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
2019-08-12 12:06:45 -07:00