Eddie Hung
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5939ffdc07
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Forgot to slice
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2019-08-23 13:06:59 -07:00 |
Eddie Hung
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242b3083ea
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Cope with possibility that D could connect to Q on same cell
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2019-08-23 13:06:31 -07:00 |
Eddie Hung
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18b64609c2
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xilinx_srl to use 'slice' features of pmgen for word level
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2019-08-23 12:22:06 -07:00 |
Eddie Hung
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f4fd41d5d2
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Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
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2019-08-23 11:35:06 -07:00 |
Clifford Wolf
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55bf8f69e0
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Fix port hanlding in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-23 16:26:54 +02:00 |
Clifford Wolf
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adb81ba386
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Add pmgen slices and choices
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-23 16:15:50 +02:00 |
Eddie Hung
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6e8fda8bf0
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Add doc
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2019-08-22 11:52:24 -07:00 |
Eddie Hung
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cabadb85e2
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Add copyright
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2019-08-22 11:25:19 -07:00 |
Eddie Hung
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9f3ed1726e
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pmgen to also iterate over all module ports
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2019-08-22 11:15:16 -07:00 |
Eddie Hung
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74bd190d3b
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Remove output_bits
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2019-08-22 11:14:59 -07:00 |
Eddie Hung
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231ddbf95c
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Forgot to set ud_variable.minlen
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2019-08-22 11:02:17 -07:00 |
Eddie Hung
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61639d5387
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Do not run xilinx_srl_pm in fixed loop
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2019-08-22 10:51:04 -07:00 |
Eddie Hung
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d0b2973413
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
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2019-08-22 10:32:06 -07:00 |
Eddie Hung
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7d02d17b16
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Reuse var
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2019-08-21 19:18:40 -07:00 |
Eddie Hung
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5c8344363f
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Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b .
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2019-08-21 19:18:27 -07:00 |
Eddie Hung
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7e7965ca7b
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Trim shiftx_width when upper bits are 1'bx
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2019-08-21 18:43:17 -07:00 |
Eddie Hung
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ed7be3e6b6
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Add comment
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2019-08-21 17:36:38 -07:00 |
Eddie Hung
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15188033da
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Add variable length support to xilinx_srl
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2019-08-21 17:34:40 -07:00 |
Eddie Hung
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6d76ae4c65
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Rename pattern to fixed
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2019-08-21 15:46:58 -07:00 |
Eddie Hung
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b0a3b430bf
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attribute -> attr
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2019-08-21 15:44:07 -07:00 |
Eddie Hung
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61b4d7ae13
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Use Cell::has_keep_attribute()
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2019-08-21 15:41:46 -07:00 |
Eddie Hung
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6fa9e03e4c
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xilinx_srl to support FDRE and FDRE_1
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2019-08-21 15:35:29 -07:00 |
Eddie Hung
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3c8e8521a6
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Fix polarity of EN_POL
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2019-08-21 14:42:11 -07:00 |
Eddie Hung
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a980f0d4be
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Add CLKPOL == 0
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2019-08-21 14:35:40 -07:00 |
Eddie Hung
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1c7d721558
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Reject if not minlen from inside pattern matcher
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2019-08-21 14:26:24 -07:00 |
Eddie Hung
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cab2bd083e
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Get wire via SigBit
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2019-08-21 13:47:47 -07:00 |
Eddie Hung
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52fea5b658
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Respect \keep on cells or wires
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2019-08-21 13:42:03 -07:00 |
Eddie Hung
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5ce0c31d0e
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Add init support
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2019-08-21 13:05:10 -07:00 |
Eddie Hung
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df53fe12e7
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Fix spacing
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2019-08-21 12:54:11 -07:00 |
Eddie Hung
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0250712486
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Initial progress on xilinx_srl
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2019-08-21 12:50:49 -07:00 |
Miodrag Milanovic
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948b6f91a1
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Fix test_pmgen deps
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2019-08-21 17:00:24 +02:00 |
Eddie Hung
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9b9d759451
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Fix copy-paste typo
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2019-08-20 20:18:51 -07:00 |
Clifford Wolf
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d0117d7d12
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Merge branch 'master' into clifford/pmgen
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2019-08-20 11:39:23 +02:00 |
Clifford Wolf
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1e3dd0a2da
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
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2019-08-19 13:04:06 +02:00 |
Miodrag Milanovic
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dbe3cb9708
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Ignore all generated headers for pmgen pass
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2019-08-18 10:49:17 +02:00 |
Clifford Wolf
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f3405fb048
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Refactor pmgen rollback mechanism
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-17 13:54:18 +02:00 |
Clifford Wolf
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318ae0351c
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Improvements in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-17 13:53:55 +02:00 |
Clifford Wolf
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f95853c822
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Add pmgen "fallthrough" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-17 11:29:37 +02:00 |
Eddie Hung
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cd5a372cd1
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Add help() call
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2019-08-16 13:00:12 -07:00 |
Clifford Wolf
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64bd414e54
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Minor bugfix in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-16 14:35:13 +02:00 |
Clifford Wolf
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20910fd7c8
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Add pmgen finish statement, return number of matches
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-16 14:16:35 +02:00 |
Clifford Wolf
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f45dad8220
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Redesign pmgen backtracking for recursive matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-16 13:47:50 +02:00 |
Clifford Wolf
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c710df181c
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Add pmgen "generate" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-16 13:26:36 +02:00 |
Clifford Wolf
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4a57b7e1ab
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Refactor demo_reduce into test_pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-16 11:47:51 +02:00 |
Clifford Wolf
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016036f247
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Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-15 23:02:37 +02:00 |
Clifford Wolf
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969ab9027a
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Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-15 22:48:13 +02:00 |
Clifford Wolf
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eb80d3d43f
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Change pmgen default rule to reject, switch peepopt behavior to accept
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-15 22:47:59 +02:00 |
Clifford Wolf
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03f98d9176
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Add demo_reduce pass to demonstrace recursive pattern matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-15 18:36:39 +02:00 |
Clifford Wolf
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73bf453929
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Improvements in pmgen for recursive patterns
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-15 18:35:56 +02:00 |
Eddie Hung
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12c692f6ed
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc1310 , reversing
changes made to f54bf1631f .
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2019-08-12 12:06:45 -07:00 |