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76 Commits

Author SHA1 Message Date
Eddie Hung ec88129a5c Update help message 2019-04-22 11:38:23 -07:00
Eddie Hung 0e76718720 Move 'shregmap -tech xilinx' into map_cells 2019-04-22 10:45:39 -07:00
Eddie Hung e300b1922c Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-22 10:36:27 -07:00
Clifford Wolf cf1ba46fa0 Re-added clean after techmap in synth_xilinx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 09:03:11 +02:00
Eddie Hung d342b5b135 Tidy up, fix for -nosrl 2019-04-21 15:33:03 -07:00
Eddie Hung 726e2da8f2 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-21 14:28:55 -07:00
Eddie Hung a3371e118b Merge branch 'master' into map_cells_before_map_luts 2019-04-21 14:24:50 -07:00
Eddie Hung ae95aba60a Add comments 2019-04-21 14:16:59 -07:00
Eddie Hung d99422411f Use new pmux2shiftx from #944, remove my old attempt 2019-04-21 14:16:34 -07:00
Eddie Hung 6008bb7002 Revert "synth_* with -retime option now calls abc with -D 1 as well" 
This reverts commit 9a6da9a79a.
 2019-04-18 07:59:16 -07:00
Eddie Hung 9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well 2019-04-10 08:32:53 -07:00
Eddie Hung 1d526b7f06 Call shregmap twice -- once for variable, another for fixed 2019-04-05 17:35:49 -07:00
Eddie Hung a5f33b5409 Move dffinit til after abc 2019-04-05 16:20:43 -07:00
Eddie Hung 0364a5d811 Merge branch 'eddie/fix_retime' into xc7srl 2019-04-05 15:46:18 -07:00
Eddie Hung 9758701574 Move techamp t:$_DFF_?N? to before abc call 2019-04-05 15:39:05 -07:00
Eddie Hung 8b6085254a Resolve @daveshah1 comment, update synth_xilinx help 2019-04-05 15:15:13 -07:00
Eddie Hung ff0912c75e synth_xilinx to techmap FFs after abc call, otherwise -retime fails 2019-04-05 14:43:06 -07:00
Eddie Hung 544843da71 techmap inside map_cells stage 2019-04-05 12:55:52 -07:00
Eddie Hung 7b7ddbdba7 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-04 08:13:34 -07:00
Eddie Hung e3f20b17af Missing techmap entry in help 2019-04-04 08:13:10 -07:00
Eddie Hung 572603409c Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-04 07:54:42 -07:00
Eddie Hung d9cb787391 synth_xilinx to map_cells before map_luts 2019-04-04 07:48:13 -07:00
Eddie Hung 736e19f02d t:$dff* -> t:$dff t:$dffe 2019-04-04 07:39:19 -07:00
Eddie Hung 0e2d929cea -nosrl meant when -nobram 2019-04-03 08:28:07 -07:00
Eddie Hung 88630cd02c Disable shregmap in synth_xilinx if -retime 2019-04-03 07:14:20 -07:00
Eddie Hung f9fb05cf66 synth_xilinx to use shregmap with -minlen 3 2019-03-25 13:18:55 -07:00
Eddie Hung 4cc6b3e942 Add '-nosrl' option to synth_xilinx 2019-03-21 15:04:44 -07:00
Eddie Hung ae2a625d05 Restore original synth_xilinx commands 2019-03-19 16:14:08 -07:00
Eddie Hung 24553326dd Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-19 13:11:30 -07:00
Clifford Wolf fe1fb1336b Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-19 20:30:28 +01:00
Eddie Hung 29a8d4745e Cleanup synth_xilinx 2019-03-15 23:01:40 -07:00
Eddie Hung 06f8f2654a Working 2019-03-15 19:13:40 -07:00
Eddie Hung af5706c2a3 Misspell 2019-03-14 09:06:56 -07:00
Eddie Hung 8af9979aab Revert "Add shregmap -init_msb_first and use in synth_xilinx" 
This reverts commit 26ecbc1aee.
 2019-03-14 09:01:48 -07:00
Eddie Hung f1a8e8a480 Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
Eddie Hung 26ecbc1aee Add shregmap -init_msb_first and use in synth_xilinx 2019-03-14 08:10:02 -07:00
Eddie Hung edca2f1163 Move shregmap until after first techmap 2019-03-13 17:13:52 -07:00
Clifford Wolf bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream 
Changes required for VPR place and route in synth_xilinx
 2019-03-05 15:33:19 -08:00
Clifford Wolf 13844c7658 Use "write_edif -pvector bra" for Xilinx EDIF files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 15:16:13 -08:00
Keith Rothman 5ebeca12eb Use singular for disabling of DRAM or BRAM inference. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:35:14 -08:00
Keith Rothman eccaf101d8 Modify arguments to match existing style. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:14:27 -08:00
Keith Rothman 3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Eddie Hung fe4d6898de synth_xilinx to call shregmap with enable support 2019-02-28 11:17:13 -08:00
Eddie Hung 68f38f2ee0 synth_xilinx to use shregmap with -params too 2019-02-28 10:21:05 -08:00
Eddie Hung c9ab18889a synth_xilinx to now have shregmap call after dff2dffe 2019-02-28 09:32:29 -08:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Tim 'mithro' Ansell b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
 2018-10-08 16:52:12 -07:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Clifford Wolf 6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00