riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2,723 Commits 92 Branches 49 Tags 38 MiB
Commit Graph

451 Commits

Author SHA1 Message Date
Clifford Wolf a7ab9172f9 Small corrections to const2ast warning messages 2015-08-17 16:22:53 +02:00
Florian Zeitz 0491042849 Check base-n literals only contain valid digits 2015-08-17 15:37:33 +02:00
Florian Zeitz 64ccbf8510 Warn on literals exceeding the specified bit width 2015-08-17 15:27:35 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Larry Doolittle 022f570563 Keep gcc from complaining about uninitialized variables 2015-08-14 23:26:49 +02:00
Clifford Wolf 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf 45ee2ba3b8 Fixed handling of [a-fxz?] in decimal constants 2015-08-11 11:32:37 +02:00
Marcus Comstedt c836faae3e Add -noautowire option to verilog frontend 2015-08-01 12:16:54 +02:00
Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf 4513ff1b85 Fixed nested mem2reg 2015-07-29 16:37:08 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 13983e8318 Fixed handling of parameters with reversed range 2015-06-08 14:03:06 +02:00
Clifford Wolf 99b8746d27 Fixed signedness of genvar expressions 2015-05-29 20:08:00 +02:00
Clifford Wolf 08a4af3cde Improvements in BLIF front-end 2015-05-24 08:03:21 +02:00
Clifford Wolf 6061b7bd58 bugfix in blif front-end 2015-05-18 11:15:49 +02:00
Clifford Wolf 3ecb2bf067 Improved .latch support in BLIF front-end 2015-05-17 18:58:24 +02:00
Clifford Wolf 2cc4e75914 Added read_blif command 2015-05-17 15:25:03 +02:00
Clifford Wolf e5116eeb77 Generalized blifparse API 2015-05-17 15:10:37 +02:00
Clifford Wolf 7dad017c9c abc/blifparse files reorganization 2015-05-17 14:44:28 +02:00
Clifford Wolf 61512b6f41 Verific build fixes 2015-05-17 08:19:52 +02:00
Clifford Wolf 7ff802e199 Verilog front-end: define `BLACKBOX in -lib mode 2015-04-19 21:30:46 +02:00
Clifford Wolf a923a63a89 Ignore celldefine directive in verilog front-end 2015-03-25 19:46:12 +01:00
Clifford Wolf 422794c584 Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker() 2015-03-01 11:20:22 +01:00
Clifford Wolf 1f1deda888 Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
Clifford Wolf d5ce9a32ef Added deep recursion warning to AST simplify 2015-02-20 10:33:20 +01:00
Clifford Wolf dc1a0f06fc Parser support for complex delay expressions 2015-02-20 10:21:36 +01:00
Clifford Wolf e0e6d130cd YosysJS stuff 2015-02-19 13:36:54 +01:00
Clifford Wolf c2ba4fb2fd Convert floating point cell parameters to strings 2015-02-18 23:35:23 +01:00
Clifford Wolf e9368a1d7e Various fixes for memories with offsets 2015-02-14 14:21:15 +01:00
Clifford Wolf 7f1a1759d7 Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
Clifford Wolf a8e9d37c14 Creating $meminit cells in verilog front-end 2015-02-14 10:49:30 +01:00
Clifford Wolf ef151b0b30 Fixed handling of "//" in filenames in verilog pre-processor 2015-02-14 08:41:03 +01:00
Clifford Wolf cd919abdf1 Added AstNode::simplify() recursion counter 2015-02-13 12:33:12 +01:00
Clifford Wolf 4f68a77e3f Improved read_verilog support for empty behavioral statements 2015-02-10 12:17:29 +01:00
Clifford Wolf 234a45a3d5 Ignore explicit assignments to constants in HDL code 2015-02-08 00:58:03 +01:00
Clifford Wolf c8305e3a6d Fixed a bug with autowire bit size 
(removed leftover from when we tried to auto-size the wires)
 2015-02-08 00:48:23 +01:00
Clifford Wolf 2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf df9d096a7d Ignoring more system task and functions 2015-01-15 13:08:19 +01:00
Clifford Wolf a588a4a5c9 Fixed handling of "input foo; reg [0:0] foo;" 2015-01-15 12:53:12 +01:00
Clifford Wolf 8e8e791fb5 Consolidate "Blocking assignment to memory.." msgs for the same line 2015-01-15 12:41:52 +01:00
Fabio Utzig fff6f00b3c Enable bison to be customized 2015-01-08 09:56:20 -02:00
Clifford Wolf 1bd67d792e Define YOSYS and SYNTHESIS in preproc 2015-01-02 17:11:54 +01:00
Clifford Wolf eefe78be09 Fixed memory->start_offset handling 2015-01-01 12:56:01 +01:00
Clifford Wolf 0bb6b24c11 Added global yosys_celltypes 2014-12-29 14:30:33 +01:00
Clifford Wolf 90bc71dd90 dict/pool changes in ast 2014-12-29 03:11:50 +01:00
Clifford Wolf 137f35373f Changed more code to dict<> and pool<> 2014-12-28 19:24:24 +01:00
Clifford Wolf 7751c491fb Improved some warning messages 2014-12-27 03:40:27 +01:00
Clifford Wolf 12ca6538a4 Fixed mem2reg warning message 2014-12-27 03:26:30 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 1282a113da Fixed supply0/supply1 with many wires 2014-12-11 13:56:20 +01:00
Clifford Wolf 76c83283c4 Fixed minor bug in parsing delays 2014-11-24 14:48:07 +01:00
Clifford Wolf 56c7d1e266 Fixed two minor bugs in constant parsing 2014-11-24 14:39:24 +01:00
Clifford Wolf 87333f3ae2 Added warning for use of 'z' constants in HDL 2014-11-14 19:59:50 +01:00
Clifford Wolf 4e5350b409 Fixed parsing of nested verilog concatenation and replicate 2014-11-12 19:10:35 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf acf010d30d Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions 2014-11-08 11:38:44 +01:00
Clifford Wolf a21481b338 Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." 2014-10-30 14:01:02 +01:00
Clifford Wolf 37aa2e02db AST simplifier: optimize constant AST_CASE nodes before recursively descending 2014-10-29 08:29:51 +01:00
Clifford Wolf f9c096eeda Added support for task and function args in parentheses 2014-10-27 13:21:57 +01:00
Clifford Wolf c4a2b3c1e9 Improvements in $readmem[bh] implementation 2014-10-26 23:29:36 +01:00
Clifford Wolf 70b2efdb05 Added support for $readmemh/$readmemb 2014-10-26 20:33:10 +01:00
Clifford Wolf 26cbe4a4e5 Fixed constant "cond ? string1 : string2" with strings of different size 2014-10-25 18:23:53 +02:00
Clifford Wolf c5eb5e56b8 Re-introduced Yosys::readsome() helper function 
(f.read() + f.gcount() made problems with lines > 16kB)
 2014-10-23 10:58:36 +02:00
Clifford Wolf 750c615e7f minor indenting corrections 2014-10-19 18:42:03 +02:00
Parviz Palangpour de8adb8ec5 Builds on Mac 10.9.2 with LLVM 3.5. 2014-10-19 11:14:43 -05:00
Clifford Wolf 84ffe04075 Fixed various VS warnings 2014-10-18 15:20:38 +02:00
William Speirs 31267a1ae8 Header changes so it will compile on VS 2014-10-17 11:41:36 +02:00
William Speirs fda52f05f2 Wrapped math in int constructor 2014-10-17 11:28:14 +02:00
Clifford Wolf 3838856a9e Print "SystemVerilog" in "read_verilog -sv" log messages 2014-10-16 10:31:54 +02:00
Clifford Wolf 6b05a9e807 Fixed handling of invalid array access in mem2reg code 2014-10-16 00:44:23 +02:00
Clifford Wolf f65e1c309f Updated .gitignore file for ilang and verilog frontends 2014-10-15 01:14:38 +02:00
Clifford Wolf c3e9922b5d Replaced readsome() with read() and gcount() 2014-10-15 01:12:53 +02:00
William Speirs fad0b0c506 Updated lexers & parsers to include prefixes 2014-10-15 00:48:19 +02:00
Clifford Wolf 0b9282a779 Added make_temp_{file,dir}() and remove_directory() APIs 2014-10-12 12:11:57 +02:00
Clifford Wolf b1596bc0e7 Added run_command() api to replace system() and popen() 2014-10-12 10:57:15 +02:00
Clifford Wolf 35fbc0b35f Do not the 'z' modifier in format string (another win32 fix) 2014-10-11 11:42:08 +02:00
Clifford Wolf 8263f6a74a Fixed win32 troubles with f.readsome() 2014-10-11 11:36:22 +02:00
Clifford Wolf 0a651f112f Disabled vhdl2verilog command for win32 builds 2014-10-11 10:46:19 +02:00
Clifford Wolf bbd808072b Added format __attribute__ to stringf() 2014-10-10 17:22:08 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf 48b00dccea Another $clog2 bugfix 2014-09-08 12:25:23 +02:00
Clifford Wolf 680eaaac41 Fixed $clog2 (off by one error) 2014-09-06 19:31:04 +02:00
Clifford Wolf deff416ea7 Fixed assignment of out-of bounds array element 2014-09-06 17:58:27 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf 58367cd87a Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore 2014-08-23 15:14:58 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 98442e019d Added emscripten (emcc) support to build system and some build fixes 2014-08-22 16:20:22 +02:00
Clifford Wolf e218f0eacf Added support for non-standard <plugin>:<c_name> DPI syntax 2014-08-22 14:30:29 +02:00
Clifford Wolf 74af3a2b70 Archibald Rust and Clifford Wolf: ffi-based dpi_call() 2014-08-22 14:22:09 +02:00
Clifford Wolf ad146c2582 Fixed small memory leak in ast simplify 2014-08-21 17:33:40 +02:00
Clifford Wolf 6c5cafcd8b Added support for DPI function with different names in C and Verilog 2014-08-21 17:22:04 +02:00
Clifford Wolf 085c8e873d Added AstNode::asInt() 2014-08-21 17:11:51 +02:00
Clifford Wolf 490d7a5bf2 Fixed memory leak in DPI function calls 2014-08-21 13:09:47 +02:00
Clifford Wolf 7bfc4ae120 Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
Clifford Wolf 38addd4c67 Added support for global tasks and functions 2014-08-21 12:42:28 +02:00