(clock -> clock_core in caravel_clocking, VPWR -> vccd_core and
VGND -> vssd_core in the instances of modules that were pulled from
the management SoC to the top level).
longer in the PDK but have been folded into larger library files.
With the most recent push to open_pdks to fix an error in the I/O
verilog library, the verilog testbenches once again pass.
deleted "resetb_core_h" port label. Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
layouts. Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell. These
internal lines were previously in the power routing cells.
makes backup copies of caravel and caravan layouts and replaces the
cell name of any gpio defaults block that is changed from the
contents of user_defines.v. NOTE: user_defines.v ultimately must
reside in the user project. The Makefile should copy the user's
version into the caravel directory space before running the script,
or else the script should be rewritten to reference the user's
project area when reading user_defines.v.
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file. Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
three parameterized values used in the RTL verilog. Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping. (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins. The load pin propagates through the chaing like the
other two. Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
continuous ring of vccd and vssd. The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
Tim Edwards
manarabdelaty