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  • 924b3d51de correct dummy stdcell verilog pointer Kevin Liao 2021-01-26 15:45:59 -0800
  • 965fbdbfea correct to sky130_fd_sc_hd__sdfrtp_1 Kevin Liao 2021-01-26 15:36:33 -0800
  • f7feca6686 update header for description Kevin Liao 2021-01-26 10:10:35 -0800
  • f0050b851d QuickLogic physical ccff Kevin Liao 2021-01-26 09:43:53 -0800
  • 84c217bc56 replace CFGSDFFR with QL_CCFF and fix testbench related Kevin Liao 2021-01-26 09:41:23 -0800
  • d2240d8539
         Merge pull request #86 from lnis-uofu/k4_N8_interface liaokevin-ql 2021-01-25 10:38:13 -0800
  • 78e2a242b3 Merge remote-tracking branch 'origin/master' into ganesh_dev fpga3232_qlsofa_hd_physical Ganesh Gore 2021-01-25 11:04:28 -0700
  • 0b855869bc add clock buffer tile Tarachand Pagarani 2021-01-21 23:55:52 -0800
  • f1eb4c4f88 rename module name to IO from EMBEDDED_IO_HD k4_N8_interface Kevin Liao 2021-01-21 20:52:16 -0800
  • f7af0b40cf rename prefix for circuit_model iopad Kevin Liao 2021-01-21 20:50:00 -0800
  • 9c1b2ca4d4 update the name of IO cell and ports to be consistent with QL names Tarachand Pagarani 2021-01-21 04:18:25 -0800
  • 658edb47f7
         Merge pull request #89 from lnis-uofu/custom_yosys_scr tpagarani 2021-01-21 06:58:01 -0500
  • c34c777409 Using custom yosys script for benchmarks run in generate_testbench task Lalit Sharma 2021-01-20 21:18:38 -0800
  • 3085cf7c2c remove io clk from output mux till prepack in VPR is updated to ignore physical mode Tarachand Pagarani 2021-01-20 01:16:59 -0800
  • cbb7e020e8
         Merge pull request #88 from lnis-uofu/xt_dev ganeshgore 2021-01-19 22:47:05 -0700
  • 36739d9c7c Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface Tarachand Pagarani 2021-01-17 23:55:54 -0800
  • 72d8d20356 1. Add 4 clocks to IO interfaces 2. Mux the clock with the output for sending the clock out of the FPGA Tarachand Pagarani 2021-01-17 23:54:39 -0800
  • d316f5cf21 Merge branch 'master' into xt_dev tangxifan 2021-01-15 17:39:52 -0700
  • 851aa6e07d [Doc] Minor fix on the waveform display for I/O circuitry tangxifan 2021-01-15 17:08:10 -0700
  • 69ed6b5e27 forgot to add new port, IO_ISOL_N, for EMBEDDED_IO_HD Kevin Liao 2021-01-15 12:48:32 -0800
  • f428234df8 correct EMBEDDED_IO_HD verilog pointer Kevin Liao 2021-01-15 11:08:43 -0800
  • ac355c370d merge latest changes from master Tarachand Pagarani 2021-01-15 00:26:25 -0800
  • 6f0dc05ffa
         Merge pull request #87 from lnis-uofu/multiple_global_clocks tpagarani 2021-01-15 02:34:21 -0500
  • 70d0ecdcac Added files to sync Ganesh Gore 2021-01-15 00:10:53 -0700
  • 806303af11 remove soft_adder, and fix Test_en from ccff Kevin Liao 2021-01-14 20:14:04 -0800
  • 742d16ec39 new revised isolation io logic Kevin Liao 2021-01-14 20:11:21 -0800
  • 3f5409eee2 add 4 global clocks multiple_global_clocks Tarachand Pagarani 2021-01-14 02:28:07 -0800
  • ba34ebb4e5 Removing commented sections/attributes. Also corrected indentation Lalit Sharma 2021-01-13 00:48:03 -0800
  • 6702de4516 Merging latest changes from master related to tile_port deprecation Lalit Sharma 2021-01-12 22:33:04 -0800
  • 40ddcdff67
         Merge pull request #85 from lnis-uofu/update_tile_port tpagarani 2021-01-13 01:22:45 -0500
  • 51f11ee630 Replacing deprecated tile_port syntax Lalit Sharma 2021-01-12 21:33:53 -0800
  • e06fdd0a48 add annotation to support soft_adder mode Kevin Liao 2021-01-12 21:21:53 -0800
  • e330b19408 Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface Kevin Liao 2021-01-12 21:15:15 -0800
  • be47862b87 created for quicklogic special io logic Kevin Liao 2021-01-12 21:14:09 -0800
  • ef4e064838 Updating openfpga with Kevin's changes done related to IO interface with an option of registered and non-registered IOs Lalit Sharma 2021-01-12 11:06:29 +0530
  • 489e370390 init Kevin Liao 2021-01-11 21:11:12 -0800
  • 8f1bdc2e87 Updating interface definition for QL k4_N8 device Lalit Sharma 2021-01-11 23:20:49 +0530
  • e82d2bf0d1
         Merge pull request #84 from lnis-uofu/update_task_conf tpagarani 2021-01-07 07:59:54 -0500
  • 4128f4cd1b Enabling custom yosys script only for and gate design, will enable later for other designs when yosys submodule is updated Lalit Sharma 2021-01-07 01:15:41 -0800
  • 847d0ec8f6 Adding io_reg related simple design Lalit Sharma 2021-01-06 23:24:34 -0800
  • 9b3cd1f5ff Updating task template file by calling synth_quicklogic inside yosys Lalit Sharma 2021-01-06 23:19:20 -0800
  • f3f4947395 Updating interface definition in vpr_arch.xml as suggested by Kevin as well as making related changes in openfpga.xml file Lalit Sharma 2021-01-06 23:02:16 -0800
  • 4e5798efc0 Adding custom yosys script to use synth_quicklogic while running yosys Lalit Sharma 2021-01-06 20:43:17 -0800
  • b3f001c3fa
         Merge pull request #81 from lnis-uofu/ql_ap3_arch_eval tangxifan 2021-01-06 11:08:10 -0700
  • f5c8e89c38 Adding a simple design to verify if registred io are used Lalit Sharma 2021-01-06 01:16:26 -0800
  • 30e1d846f0 Updating port names for IO pb_type as these are changed as per the latest definition Lalit Sharma 2021-01-06 01:07:15 -0800
  • a4109a66a7 Updating IO definition as per the latest changes by using 2 FF separately for input & ouput Lalit Sharma 2021-01-06 00:57:08 -0800
  • 1a4b1bc6b4 Disable generation of formal verification testbench due to disk space limitation on github actions. Disable testcase not fitting on 32x32 device ql_ap3_arch_eval Tarachand Pagarani 2021-01-05 19:44:08 -0800
  • b0c419bc72 Updating IO interface definition as well as updating its physical mode Lalit Sharma 2021-01-05 03:55:36 -0800
  • 321f1ef0ad Updating interface definition, removed in_buff, out_buff, in_reg and out_reg pb_types/models. Instead using inbuilt .input/.output/.latch and defining pack_pattern to identify reg or buff input/output. Lalit Sharma 2021-01-04 04:21:31 -0800
  • f04e72b5b3 create a copy of cout to connect to regular routing Tarachand Pagarani 2020-12-30 06:02:51 -0800
  • 8675eec9c0 Adding interface definition for registered IOs Lalit Sharma 2020-12-30 16:20:23 +0530
  • 473e1d68a6 fix the carry in dangling Tarachand Pagarani 2020-12-29 19:04:56 -0800
  • 61facff870 fix the carry in dangling and carry out accessible to regular routing Tarachand Pagarani 2020-12-29 18:54:48 -0800
  • cbe50535ca further changes in architecture to make io interfaces routable Tarachand Pagarani 2020-12-28 08:35:17 -0800
  • 465fcbc240 Merge branch 'ganesh_dev' of github.com:lnis-uofu/SOFA into ganesh_dev Ganesh Gore 2020-12-27 01:02:27 -0700
  • 474ed9b2ff Merge remote-tracking branch 'origin/master' into ql_ap3_arch_eval Tarachand Pagarani 2020-12-26 23:57:23 -0800
  • 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture Tarachand Pagarani 2020-12-26 23:29:13 -0800
  • 1aa0ef68e4 incoporated changes based on feedback from xifan Tarachand Pagarani 2020-12-24 23:05:47 -0800
  • 054c3d5f28 Updating conf file to run custom yosys script on a benchmark design lnsharma_dev Lalit Sharma 2020-12-23 00:54:56 -0800
  • 6428539dcb
         Merge pull request #80 from lnis-uofu/ganesh_dev tangxifan 2020-12-22 08:15:29 -0700
  • d4b4676ec8
         Merge pull request #79 from lnis-uofu/xt_dev tangxifan 2020-12-22 08:15:14 -0700
  • e1a25d61dc [QLSOFA] Bugfix to fix floating cin net Ganesh Gore 2020-12-22 00:22:29 -0700
  • 562641ed4d [SOFA-CHD] Bugfix to fix floating cin net Ganesh Gore 2020-12-22 00:09:46 -0700
  • 6a6b89e7b8 [Arch] Critical patch on dangling nets in logic elements tangxifan 2020-12-21 22:23:41 -0700
  • eba3827b77
         Merge pull request #78 from lnis-uofu/xt_dev tangxifan 2020-12-21 13:16:33 -0700
  • 81a31ea022 [Doc] Update documentation with latest GDS view tangxifan 2020-12-21 12:37:19 -0700
  • 01fabc65cc added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback Tarachand Pagarani 2020-12-21 07:13:38 -0800
  • 16eff30a8e [Actions] Synced LVS netlist files Ganesh Gore 2020-12-20 20:22:53 -0700
  • f494c31ca0 [Action] More cleanup while precheck Ganesh Gore 2020-12-20 17:04:56 -0700
  • e2c33f1ab3
         Merge pull request #77 from lnis-uofu/ganesh_dev tangxifan 2020-12-20 12:11:58 -0700
  • 6ef27d5399 [Cleanup] Removed old task and verilog directories Ganesh Gore 2020-12-20 10:50:13 -0700
  • c36e8d797a Updated all the results Ganesh Gore 2020-12-20 03:44:00 -0700
  • 55acf06335 Updated design with new GDS nad updated verilog netlist Ganesh Gore 2020-12-20 03:31:26 -0700
  • 5bb8adb448 [Cleanup] Converted .gds to .gds.gz Ganesh Gore 2020-12-20 02:12:31 -0700
  • da4ae780a9 [Cleanup] Converted .spef to .spef.gz Ganesh Gore 2020-12-20 02:10:51 -0700
  • 694afdf3d0 Merge remote-tracking branch 'origin/master' into ganesh_dev Ganesh Gore 2020-12-20 02:02:35 -0700
  • 894378c6a7
         Merge pull request #76 from lnis-uofu/xt_dev tangxifan 2020-12-18 20:59:33 -0700
  • 82da5dd0b0 [HDL] Update code generator for the changes on custom cell names tangxifan 2020-12-18 20:25:50 -0700
  • c523d968c7 [HDL] Bug fix due to custom cell name changing tangxifan 2020-12-18 20:24:55 -0700
  • 1eac22feba [Testbench] Critical bug fix on Caravel Testbench: Add a sufficient long waiting time for Caravel to finish its I/O configuration tangxifan 2020-12-18 20:18:02 -0700
  • 8a31edb40e [Testbench] Remove compressed testbench file tangxifan 2020-12-18 19:52:52 -0700
  • 03316d6e65 [Testbench] Remove signal initialization which is not neccessary for caravel tests tangxifan 2020-12-18 19:51:54 -0700
  • e17d51aa9f [Testbench] Bug fix in using power pins tangxifan 2020-12-18 17:49:16 -0700
  • e02d830abb Merge branch 'master' into xt_dev tangxifan 2020-12-18 17:41:33 -0700
  • f028437fef [Testbench] Update SCFF test to be compatible with simulation with power pins tangxifan 2020-12-18 16:24:56 -0700
  • 9e60f62299 [Testbench] Critical bug fix on the caravel testbench for and2_latch benchmark tangxifan 2020-12-18 16:23:50 -0700
  • 7b2632a872 [Testbench] Add power pin support to scff testbench tangxifan 2020-12-18 15:55:05 -0700
  • 2b0294e40a [Testbench] Recover from LFS tangxifan 2020-12-18 15:39:00 -0700
  • f258cefd9a [QLSOFA-HD] Patch on lvs netlist tangxifan 2020-12-18 10:55:17 -0700
  • 7ea8f77038 [Testbench] Add include netlist for caravel testbench tangxifan 2020-12-17 20:20:39 -0700
  • 187364ebc3 [Testbench] Add Caravel testbench for and2_testbench tangxifan 2020-12-17 20:19:12 -0700
  • 5da9696e63
         Merge pull request #74 from lnis-uofu/xt_dev tangxifan 2020-12-17 16:25:37 -0700
  • 2a429178c7
         Merge pull request #75 from lnis-uofu/ganesh_dev tangxifan 2020-12-17 16:24:43 -0700
  • fa0ae58192 [Actions] Removed HD action Ganesh Gore 2020-12-17 15:29:18 -0700
  • 85a59e4673 [CI] Precheck related updates Ganesh Gore 2020-12-17 15:01:49 -0700
  • d6b435018c [Testbench] Rename top modules of Caravel testbenches to be compatible with scripted verification flow tangxifan 2020-12-17 10:45:33 -0700
  • 46bd96f8e9 [Testbench] Add carevel testbench for ccff test tangxifan 2020-12-17 10:45:06 -0700
  • d019166190 [Testbench] Bug fix in Caravel ccff testbench tangxifan 2020-12-17 10:36:25 -0700
  • 37bca4684b [BugFix] After Integration with mpw-one-b Ganesh Gore 2020-12-17 09:29:54 -0700