Adding io_reg related simple design

BENCHMARK/io_reg/io_reg.v

@@ -0,0 +1,22 @@
+module io_reg(clk, in, out);
+
+    input clk;
+    input in;
+    output out;
+    reg out;
+
+    //reg temp;
+
+    always @(posedge clk)
+    begin
+        out <= in;
+    end
+    
+    /*always @(posedge clk)
+    begin
+        out <= temp ;
+    end*/
+    
+endmodule
+
+

BENCHMARK/io_reg/io_reg_tb.v

@@ -0,0 +1,21 @@
+module io_reg_tb;
+    
+    reg clk_gen, in_gen;
+    wire out;
+
+    io_reg inst(.clk(clk_gen), .in(in_gen), .out(out));
+
+    initial begin
+        #0 in_gen = 1'b1; clk_gen = 1'b0;
+        #100 in_gen = 1'b0;
+    end
+
+    always begin
+        #10 clk_gen = ~clk_gen;
+    end
+
+    initial begin
+        #5000 $stop;
+    end
+
+endmodule

SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf

@@ -39,7 +39,7 @@ bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
 bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
 bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
 bench8=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cavlc_top/rtl/*.v
-bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v
+#bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v
 bench10=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter120bitx5/rtl/*.v
 bench11=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter_16bit/rtl/*.v
 bench12=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/dct_mac/rtl/*.v
@@ -69,7 +69,7 @@ bench5_top = rs_decoder_top
 bench6_top = top_module
 bench7_top = and2_or2
 bench8_top = cavlc_top
-bench9_top = cf_fft_256_8
+#bench9_top = cf_fft_256_8
 bench10_top = counter120bitx5
 bench11_top = top
 bench12_top = dct_mac