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[Testbench] Rename top modules of Caravel testbenches to be compatible with scripted verification flow

This commit is contained in:
tangxifan 2020-12-17 10:45:33 -07:00
parent 46bd96f8e9
commit d6b435018c
2 changed files with 2 additions and 2 deletions
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2
TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v
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@ -6,7 +6,7 @@
`define FPGA_PROG_CLOCK_PERIOD 12.5
`define FPGA_CLOCK_PERIOD 12.5
module ccff_test_caravel;
module ccff_test_post_pnr_caravel_autocheck_top_tb;
reg clock;
reg RSTB;
reg power1, power2;

2
TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v
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@ -5,7 +5,7 @@
`define SOC_CLOCK_PERIOD 12.5
`define FPGA_CLOCK_PERIOD 12.5
module scff_test_caravel;
module scff_test_post_pnr_caravel_autocheck_top_tb;
reg clock;
reg RSTB;
reg power1, power2;